Strange component in quartus RTL viewer using verilog

Question

I'm learning verilog, and when i don't know how a circuit will work just looking in the verilog code, I go to RTL viewer to see the digital logic. But in this code a strange component appears and I don't know what is this component. Is a flip-flop, mux or a logic port? below is the code and an image, in the image , the component is the red triangle.

The code :

module testesoma(clock,reset,in, out,aux);

input wire reset, clock, in ;
output reg [3:0] out,aux;


 always @(posedge clock or posedge reset)
begin
    if(reset)
        begin
            out = 0;
        end
    else    
        out = aux;
        aux = aux + 1;
end
endmodule

Answer 1

What a great schematic: +1 for going to the trouble of generating it. You've got multiple issues with your code, and this is a great example of the dangers of using blocking assignments, feedback, not using synthesis templates, and so on. Quartus has certainly screwed up, but it's not surprising given the input. Issues:

1. don't use blocking assignments here - use <=
2. sort out your begins and ends. As a staring point, don't put any begin/end in your code unless it's necessary; it's verbose, and hides errors like this. Only use begin/end when you explicitly need to make a multi-stament block. Note that aux=aux+1 is outside your clocked if/else statement - when is it meant to execute?
3. Sort out where and when you want aux to increment.
4. Be very careful when you have feedback like aux=aux+1. If you're not careful, the real hardware will oscillate.
5. don't write chained logic like this - start to think parallel.

Quartus has had a fairly good go, but the circuit it has produced will just oscillate, and the aux output is not clocked, which was presumably your intention. Quartus has put in the red buffer because it can see that it has produced an unstable feedback circuit, and it's had a half-hearted go at breaking it. It should have produced a warning somewhere about this.

1 - rewrite your code; something like

    always @(posedge clock or posedge reset)
       if(reset)
          out <= 0;
        else    
          out <= aux;

   always @(posedge clock or posedge reset)
       if(reset)
          aux <= 0;
        else    
          aux <= aux + 1'b1;

2 - don't assign to multiple variables in a clocked always unless/until you understand what can go wrong with it (hint: check all branches/execution paths, confirm that something logical happens to all variables you assign to in all possible paths)

3 - Find a book on VHDL, read the chapter on delta delays/assignments, and your Verilog will be much better.

Answer 2

That symbol is just a buffer, which drives the output equal to the input. As to why it would be appearing in a digital logic schematic, I'm not sure.

Buffers don't have any impact on the digital functioning of a circuit, they are inserted by synthesizers when the capacitance of a net is too large for the driver cell to drive efficiently. You can mostly ignore it.

Also I am a little suspicious of that schematic, it doesn't appear to match your RTL. The rtl increments aux on every posedge clock, but that is showing a combinational feedback loop through the adder, which doesn't seem like it would work at all.