In modern, high-performance, generally available CPUs (read, x86), the N-bit architectural distinction refers to width of the data operated upon by the architecturally preferred integer operations. These CPUs contain registers of many different sizes, however, some which can pack multiple data values into one register as one would use with SIMD instructions.
The relationship between memory address space and this N-bit architectural distinction simply comes from the fact that once 32bits could fit in a single register, memory offset calculations could be performed in a single cycle, and 32bits seemed like enough address space for the foreseeable future. Eventually, that foreseeable future expired, and now we perform memory offset calculations with 64bit values in a 64bit address space.
This relationship with address space is somewhat arbitrary and was based upon that fact that these values became large enough to provide a reasonable amount of memory. In 12-bit minicomputers for example, memory was not limited to (2^12) 4096 bytes, memory address simply spanned multiple registers and offset calculations took more than once cycle. The same approach is used today with some 8-bit microcontrollers, the type you would find in a microwave oven. They may provide a 16-bit address space, 64kB of memory, by storing addresses in two registers rather than one.
So, unless you're dealing with non-mainstream CPUs, you can consider the N-bit distinction the address space. However, there are cases even today, where this doesn't map. For example microcontrollers, as mentioned, and domain specific or supercomputing architectures which may use "Very Large Instruction Words", that could be considered "2048-bit CPUs" but most likely operate in a 64-bit address space.