4-Bit verilog adder not passing carry bit

Question

I had my 2-bit adder working, except for some reason it is not passing the carry bit. For instance if I use A=1 and B=1 the result S=00, but if either A or B is 1 i get S=1 ?i tried printing out the values and it seems my c1 wire in the 2nd module isn't being set, and for some reason Cout is.

So with a input of A=1, B=1, S=00 and Cout=1 when it should be. S=10 and Cout=0

I have only been using Verilog for one day so the syntax is very new to me.

module fulladder(Cin,A,B,S,Cout); // dont forget semi colon
    input A,B, Cin; // defaults to 1 bit or [0,0] size
    output S, Cout;
    wire XOR1,AND1,AND2;

    xor(XOR1,A,B);
    and(AND1,A,B);
    xor(S,Cin,XOR1);
    and(AND2,Cin,XOR1);
    or(Cout,AND2,AND1);

endmodule

module adder4(Cin,A,B,S,Cout);
input Cin;
input [0:1]A;
input [0:1]B;
output [0:1]S;
output Cout;
wire c1;

fulladder FA1(Cin,A[0:0],B[0:0],S[0:0],c1);
fulladder FA2(c1,A[1:1],B[1:1],S[1:1],Cout);
endmodule


module t_adder;

reg Cin;
reg [1:0]A;
reg [1:0]B;// to declare size, must be on own line, wires can be more than 1 bit
wire [1:0]S;
wire Cout;
adder4 add4bit(Cin,A,B,S,Cout);

initial 
begin
    A = 1; B = 1; Cin = 0;
    #1$display("S=%b Cout = %b",S,Cout);
end

endmodule

Answer 1

You're reversing the bit order in the adder4 module, by declaring the inputs as [0:1], where elsewhere it is [1:0].

Since you reverse the bits, to adder4 it looks like you are adding A=2'b10, B=2'b10, which gives the output you see (3'b100).