Compare-and-swap is implemented in hardware; roughly speaking the processor works with the memory bus to ensure that the core executing the compare-and-swap has exclusive access to shared memory. So it is literally not possible for the two processes to run at the same time: One will be the first to get the (hardware-guaranteed) lock of the shared memory.
For instance, on Intel, atomic compare-and-swap is implemented by LOCK CMPXCHG. The LOCK prefix ensures that:
In a multiprocessor environment, the LOCK# signal ensures that the processor has exclusive use of any shared memory while the signal is asserted.
(Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z, vol 2A p. 3-462).