VHDL nested conversions

Question

The origin of the question is "what are conversion functions in VHDL?" and that question applied to my application: what would happen if I use nested conversions? More specifically, does conversion function actually create a combinational machine or is it just a clarification for synthesiser/implementer. Therefore would it be causing any timing problems if I use nested conversions, say for an absolute function. (For simplicity assume a & b has space for sign bit and will not overflow)

signal a: std_logic_vector(something); 
signal b: std_logic_vector(something);
signal c: std_logic_vector(something);
c <= to_logic_vector(abs(signed(a)-signed(b)));

Thanks, Cem

Answer 1

Conversion functions cost nothing and generate no logic.

They are purely clarification for (a) the compilers, (b) the implementer and most importantly (c) the maintainer who has to work out what you did later on.

So given the VHDL code

signal a: std_logic_vector(something); 
signal b: std_logic_vector(something);
signal c: std_logic_vector(something);
c <= std_logic_vector(abs(signed(a)-signed(b)));

there is absolutely no problem (except ugliness) with the cascaded conversions; they make it crystal clear that while a,b,c are std_logic_vector, they are to be interpreted as signed data for this expression.

And this is occasionally perfectly appropriate practice.

HOWEVER: If a,b,c always represent signed data, it would be better to declare them signed in the first place:

signal a: signed(something); 
signal b: signed(something);
signal c: signed(something);
c <= abs(a - b);

Think about the design; get the types correct, and you may find 90% of the type conversions disappear.

Oh, and I also recommend numeric_std over the non-standard alternatives.

Answer 2

You can use use ieee.numeric_std package.

http://en.wikipedia.org/wiki/Numeric_std

http://www.ece.msstate.edu/~reese/EE8993/lectures/numeric_standard.pdf