VHDL testbench report error

Question

working on a project with a self checking test bench and having a problem I do not understand.

The problem for the following code is an error in the simulation. I will point to where the error is coming from in the code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

ENTITY TestBenchAutomated IS
-- Generics passed in
generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
END TestBenchAutomated;

ARCHITECTURE behavior OF TestBenchAutomated IS 

     -- Component Declaration for the Unit Under Test (UUT)
     COMPONENT TopLevelM_M
     generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
     PORT(
            clk : IN  std_logic;
            next_in : IN  std_logic; --User input
            rst_in : IN  std_logic;  --User input
            OUTPUT : OUT  SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0) --Calculated DATA output
          );
     END COMPONENT;


    --Inputs
    signal clk : std_logic := '0';
    signal next_in : std_logic := '0';
    signal rst_in : std_logic := '0';

    --Outputs
    signal OUTPUT : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);

    -- Clock period definitions
    constant clk_period : time := 10 ns;

    --Variable to be used in assert section
     type Vector is record
            OUTPUT_test : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
     end record;

type VectorArray is array (natural range <>) of Vector;

constant Vectors : VectorArray := (
     -- Values to be compaired to calculated output
    (OUTPUT_test =>"000000110000"), -- 48
    (OUTPUT_test =>"000011110110"), -- 246
    (OUTPUT_test =>"000101001000"), -- 382 <--- Purposefully incorrect value, Should be '000100001000' = 264
    (OUTPUT_test =>"111111010011"), -- -45
    (OUTPUT_test =>"111101001100"), -- -180
    (OUTPUT_test =>"111111001111"), -- -49
    (OUTPUT_test =>"000000101011"), -- 43  Purposefully incorrect value, Should be '000010101011' = 171
    (OUTPUT_test =>"000000010011"), -- 19
    (OUTPUT_test =>"111111100101"), -- -27
    (OUTPUT_test =>"111110111011"), -- -69
    (OUTPUT_test =>"111110111011"), -- -69
    (OUTPUT_test =>"000000101101"), -- 45
    (OUTPUT_test =>"111011011110"), -- -290
    (OUTPUT_test =>"000001010110"), -- 86
    (OUTPUT_test =>"000011110010"), -- 242
    (OUTPUT_test =>"00000111110"),  -- 125
    (OUTPUT_test =>"111111001001"), -- -55
    (OUTPUT_test =>"000100010101"), -- 277
    (OUTPUT_test =>"111111100011"), -- -29
    (OUTPUT_test =>"111101111101"));-- -131 



BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: TopLevelM_M PORT MAP (
             clk => clk,
             next_in => next_in,
             rst_in => rst_in,
             OUTPUT => OUTPUT
          );

    -- Clock process definitions
  clk_process :process
        begin
            clk <= '0';
            wait for clk_period/2;
            clk <= '1';
            wait for clk_period/2;
        end process;
    -- Process to simulate user input and to check output is correct
Test :process
    variable  i : integer;
        begin
            wait for 100 ns;
            rst_in <= '1';
            wait for clk_period*3;
            rst_in <= '0';

    --Loops through enough times to cover matrix and more to show it freezes in S_Wait state
    for i in 0 to 50 loop 

            for i in Vectors'range loop

                next_in <= '1';
                wait for clk_period*5;
                next_in <= '0';
                wait for clk_period*4; --Appropriate amount of clock cycles needed for calculations to be displayed at output
                --Check the output is the same as expected
                assert OUTPUT = Vectors(i).OUTPUT_test
                report "Incorrect Output on vector line" & integer'image(i) &
                lf & "Expected:" & integer'image(i)(to_integer((Vectors(i).OUTPUT_test))) --& lf &
                --"But got" & integer'image(i)(to_integer(signed(OUTPUT)))
                severity error;

            end loop;
        end loop;

        wait;

    end process;
END;

As you can see in the vector, I have inserted two incorrect values to make sure the code works. I there for expect an error in the simulation telling me that there is an error on address 2 of the vector and what integer it is. However, the simulation stops and i get this:

ERROR: Index 328 out of bound 1 to 1. ERROR: In process TestBenchAutomated.vhd:Test

INFO: Simulator is stopped.

Obviously the integer 328 that is represented by the binary number in the vector causes this error, but I dont understand why it causes THIS error instead of the one I have coded. What is this index out of bound OF?

Any help would be much appreciated.

Thanks

Answer 1

This:

report "Incorrect Output on vector line" & integer'image(i) &
lf & "Expected:" & integer'image(i)(to_integer((Vectors(i).OUTPUT_test)))

Should be:

report "Incorrect Output on vector line" & integer'image(i) &
lf & "Expected:" & integer'image(to_integer((Vectors(i).OUTPUT_test)))

It's complaining that the value (to_integer((Vectors(i).OUTPUT_test))) is out of range for a character when it should have been used as parameter to 'IMAGE, which you supplied already as i.

For a simplified test case:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is
    constant m: integer := 3; 
    constant n: integer := 5; 
    constant h: integer := 4; 
    constant DATA_SIZE: integer :=5;
end entity;

architecture fum of foo is
    signal OUTPUT : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0) := "000011110110" ;

     type Vector is record
            OUTPUT_test : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
     end record;

    type VectorArray is array (natural range <>) of Vector;

    constant Vectors : VectorArray := (
         -- Values to be compaired to calculated output
        (OUTPUT_test =>"000011110110"), -- 246  (CORRECT)
        (OUTPUT_test =>"000101001000")  -- 382  (INCORRECT)        
        );

begin
TEST:
    process 
    begin
        for i in Vectors'RANGE loop
            assert OUTPUT = Vectors(i).OUTPUT_test
            report "Incorrect Output on vector line " & integer'image(i) &
--            lf & "Expected:" & integer'image(i)(to_integer((Vectors(i).OUTPUT_test)))
            lf & "Expected:" & integer'image(to_integer((Vectors(i).OUTPUT_test)))
            severity error;
        end loop;
        wait;
    end process;

end architecture;

And the incorrect usage, Nick Gasson's nvc gave:

david_koontz@Macbook: nvc -a foo.vhdl
** Error: expected 2 parameters for attribute IMAGE but have 3
File foo.vhdl, Line 34 lf & "Expected:" & integer'image(i)(to_integer((Vectors(i).OUTPUT_t ...

                             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^  

With the correct number of arguments to `'IMAGE' (shown in the example):

david_koontz@Macbook: nvc -r foo
** Fatal: 0ms+0: Assertion Error: Incorrect Output on vector line 1
Expected:328
Process :foo:test
File foo.vhdl, Line 32

Found a ghdl bug not reporting this when it likely should. It worked either way (this should be a run time error). An integer value of 382 isn't a character eligible for concatenation.

Addendum:

Tristan Gingold (ghdl author) pointed out that the expression is an element index to the string output of the 'IMAGE function.

Further analysis reveals the basis for the error message on the original code for the question:

 & integer'image(i)(to_integer((Vectors(i).OUTPUT_test)))

T'IMAGE(X)
Kind: Function. Prefix: Any scalar type or subtype T.
Parameter: An expression whose type is the base type of T.
Result Type: Type String.
Result: The string representation of the parameter value, without
leading or trailing whitespace.

No concatenation operator following.

(to_integer( ( Vectors(i).OUTPUT ) ) ) returns the integer value for the record element OUTPUT, type signed. (superfluous parentheses aside).

The contents of Vectors(i).OUTPUT is

constant Vectors : VectorArray := (
    (OUTPUT_test =>"000011110110"), -- 246  (CORRECT)
    (OUTPUT_test =>"000101001000")  -- 382  (INCORRECT)        
    );

The 382 should be 328, its 0x148. Dyslexia is hard to spell.

And in this case for i = 1 (Vectors'RANGE is (0 to 1), is "000101001000" which to_integer is 328, out of range for an element of a string (element type character).

An integer, value 328 or not is not an element index type for a record (while OUTPUT is).

The subtype for the unnamed string output of 'IMAGE is the length of the string for i, whose value is 1, the length is 1, the range is 1 to 1. 328 is out of range.

Notice the ISIM message said exactly that in the original model:

ERROR: Index 328 out of bound 1 to 1. ERROR: In process TestBenchAutomated.vhd:Test

This still looks like a ghdl error. It does also make nvc's error message suspect however.