mDDR chips used in Beagleboard xM

Question

I'm analysing the X-Loader settings for the POP mDDR on the Beagleboard xM. The amount of mDDR POP memory in the BB xM is 512MB (according to the Manual). More precisely the Micron variant: 256MB on CS0 + 256MB on CS1 = 512MB total. The bus width is 32 bits, this can be verified in the SDRC_MCFG_p register settings in the X-Loader. The type of memory used is the MT46H128M32L2KQ-5 as mentioned in this group:

https://groups.google.com/forum/#!topic/beagleboard/vgrq2bOxXrE

Reading the data sheet of that memory, the 32 bit configuration with the maximum capacity is 16Meg x 32 x 4 = 64Meg x 32. So 64MB are not 256MB, 128 MB are feasible but only with 16 bit bus width, and even then, we are still not at 256MB. The guy in the group mentioned above says that the memory is a 4Gb, but the data sheet says that it is a 2Gb.

My question: How can 512MB be achieved by using 2 memory chips of the above type and 32 bit bus width?

Thanks in advance for your help.

Martin

Answer 1

According to datasheet MT46H128M32L2KQ-5 has following configuration:

MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2

16 Meg x 32 x 4 Banks x 2 = 4096 Meg (bits, not bytes)

4096 Meg (bits) / 8 = 512 MB (Megabytes)

More from datasheet:

The 2Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic 
random-access memory containing 2,147,483,648 bits. 

Each of the x32’s 536,870,912-bit banks is organized as 16,384 rows by 1024 
columns by 32 bits. (p. 8)

So, if you multiply the number of rows by the number of columns by the number of bits (it's specified in the datasheet), you will get the size of a bank in bits. Bank size is = 16384 x 1024 x 32 = 16 Megs x 32 = 536870912 (bits).

Next, you need to multiply the bank size (in bits) by the number of banks in chip: chip size = 536870912 x 4 = 2147483648 (bits).

In order to get result in bytes, you have to dived it by 8.

chip size (bytes) = 2147483648 (bits) / 8 = 268435456

In order to get result in megabytes, you have to dived it by 1024 x 1024

chip size = 268435456 / 1024 / 1024 = 256 MB (Megabytes)

This is dual LPDDR chip internally organized as 2 x 256 MB chips (it has two chip selects: CS0#, CS1#) (it's specified in the datasheet). The single chip contains two memory chips inside, 256MB each. For BB this single chip must be configured like 2 memories 256MB each in order to get 512MB. So, you have to setup CS0 as 256MB and CS1 as 256MB.