VHDL Synthesis Error

Question

I'm trying to write some simple math functions in VHDL but I keep getting the error

found '0' definitions of operator "+", cannot determine exact overload matching definition for "+" and I also get the same error about the division.

Here is the relevant code:

    signal delay_1           : integer range 0 to 127;
--  signal delay_2           : integer range 0 to 127;
--  signal delay_3           : integer range 0 to 127;
--  signal delay_4           : integer range 0 to 127;
    signal us_clock          : std_logic;
    signal ds_squareroot     : integer range 0 to 100;
    signal ds_squared        : integer range 0 to 5000;

 if(i_reset = '1') then
        delay_1        <= 0;
        delay_2        <= 0;
        delay_3        <= 0;
        delay_4        <= 0;
        ds_squared     <= 0;
        ds_squareroot  <= 0;
    elsif(rising_edge(i_clock)) then
        -- Delay 1 calculations
        ds_squared <= (i_distance*i_distance + (speaker_distance)*(speaker_distance));
        for n in 0 to 20 loop
            ds_squareroot <=  ((50 + ds_squared/ds_squareroot)/2);
        end loop;
        delay_1 <= (ds_squareroot - i_distance)/ speed_sound;

And here are the libraries that I'm calling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;

Any advice as to why this is not compiling would be very helpful.

Answer 1

The error was that i_distance was a std_logic_vector and speaker_distance was an integer. Obviously this did not synthesize because of the difference in types here. I solved it with this simple expression

distance     <= conv_integer(i_distance);

This made both integers, which allowed the design to synthesize. Thanks for the help.