Cannot include define file in verilog

Question

I am using ModelSim to simulate Verilog. I have created one define.v file and want to include this define.v in multiple other verilog modules.

part of define.v is as follows:

// defines

`define RSIZE 4
`define ISIZE 16
`define DSIZE 16
`define ASIZE 16
`define NREG  4

`define ADD 4'b0000
`define SUB 4'b0001
`define AND 4'b0010
`define OR  4'b0011
`define SLL 4'b0100
`define SRL 4'b0101
`define SRA 4'b0110
`define RL  4'b0111
`define LW  4'b1000
`define SW  4'b1001
`define LHB 4'b1010
`define LLB 4'b1011
`define BR  4'b1100
`define JAL 4'b1101
`define JR  4'b1110
`define EXEC 4'b1111

...
...

I have include this file in multiple other modules, for instance: the alu.v

//ALU.v

`include "define.v"

module alu(
    input [`DSIZE-1:0] a, b, //operands
    input [3:0] op,          //operation code
    input [3:0] imm,         //immediate

    output reg [`DSIZE-1:0] out, //output
    output reg [2:0] flag        //flag for N, V, Z in sequence
    );
...
...

However, while compiling, it seems that the define file is not included, the error is as follows:

** Error: //psf/Home/Desktop/Projects/project1/alu.v(3): 
          Cannot open `include file "define.v".

How could I solve this problem?

Answer 1

If define.v is not within the current directory you need to instruct Modelsim to use the directory containing define.v when searching for files which are included.

The option to do this is +incdir+path.

So, for example, if you have the following file structure:

project/src/alu.v
project/include/define.v

And you run from project, then you need to include +incdir+include as an argument to Modelsim.

---

As a side note, if you are including the same file more than once, you should use "include guards" to avoid warnings about macros being redefined.

`ifndef DEFINE_V
`define DEFINE_V
  `define RSIZE 4
  `define ISIZE 16
  ....
`endif