Waiting posedge clk before doing a job? — How

Question

module DoorControl( clk, data, open,addressOftheMemory,  outp );

localparam Size_ofTheWord = 32;
input open;

input [16:0] addressOftheMemory;
input [Size_ofTheWord-1:0] data;

input clk ;
output reg outp;
reg [WordSize-1: 0] Memory [65535: 0];


always @ ( open )  // open is 1 or 0 
  if ( open  )          
     // i
     outp = Memory[addressOftheMemory];
  else if ( !open )    
     Memory[addressOftheMemory] = data;


endmodule

Line marked with (i), I want wait just posedge clk before sending outp to output port.However, When I have tried like ;

if ( posedge clk )

it gives error

while ( clk != 1 ) begin

end 

it gives absurb answer/simulation output. What thing(s) should I put to that line to wait posedge clk before sending output ?

Answer 1

You can delay execution until the clock edge like this:

always @ ( open )  // open is 1 or 0 
  if ( open  )
     @(posedge clk) outp = Memory[addressOftheMemory];
  else if ( !open )    
     Memory[addressOftheMemory] = data;

That may or may not accomplish what you want. It is not synthesizable, and the always block will not be rescheduled while it is executing or suspended, so if open toggles multiple times in a clock period, that code is probably not going to do what you want.

More background: you can specify a delay/event control on any statement, including a null statement. (e.g. in @(posedge clk);, the semicolon is a null statement.) In fact, the syntax definition of an always construct is:

always_construct: always statement

Meaning that there is nothing magical about always @(open) or always @(posedge clk), they are simply introducing a statement and specifying event control. When delay control (#) is attached to a statement, execution of the statement is deferred until a fixed time in the future. When event control (@) is attached to a statement, execution of the statement is deferred until the event condition is satisfied.

Answer 2

You have to think a little more critically about what you are trying to model. It looks like you are just trying to model a memory with "open" controlling the read/write operation.

You have asynchronous writing of data & synchronous reading of data. For memory access it is better just to have complete synchronous behavior.

always @(posedge clk) begin
if( open )
    outp = Memory[addressOftheMemory];
else
    Memory[addressOftheMemory] = data;
end