There's a combinational loop: The output of 'register' feeds back into its input through the xor/or gates in test. You've essentially created a ring oscillator.
If you add the following code inside register, you can see this happening:
always @(in) $display("@%d: in = %d", $time, in);
You'll see a bunch of these when you run the interpreter:
@ 1: in = 1
@ 1: in = 0
@ 1: in = 1
@ 1: in = 0
It looks like you're trying to make an enabled latch in 'register'. Is that what you intended? An edge triggered flip flop is the normal practice in synchronous design. You'd need two latches back-to-back to do that, but the standard (and much easier) way to do this in Verilog is like this:
reg my_flop;
always @(posedge clk)
my_flop <= input;
If you really want a latch, it can be inferred like this (but these tend to be error prone and are generally discouraged):
always @(clk, input)
begin
if (clk)
my_flop = input;
end
Is there a reason you're trying to create these manually with gates?