S-R Flip-Flops (Unlocked)

Question

The operation of S-R latches is confusing me. From what I can tell, the outputs, Q and Q' are determined by:

Q = R NOR Q'

Q' = S NOR Q

Where S and R are two input bits: set and reset.

I don't quite understand how both outputs are defined in terms of the other. How is this carried out if each output needs the value of the other output to be determined?

Answer 1

That is precisely the point of a flip-flop: Its output depends on the state of the flip-flop itself. And since all logical values have to come from some gate, this state can only be conjured up by having a feedback cycle, a gate that ultimately consumes its own input.

The most simple combination of logical gates that can store a state is this:

Q = NOT Q'
Q' = NOT Q

If you wire up two not gates like this and power them up, Q will either rise to 1 or fall to 0. What state is assumed depends on preexisting charges and chance. The only trouble with this flip-flop is that you can't influence its state from the outside.

This is why the S-R latches add the two inputs R and S to force either Q or Q' to 0. This is best illustrated with an example of the latch operation that changes its state from Q = 0 to Q = 1:

• Start with the wires at

  R = 0, S = 0, Q = 0, Q' = 1
  

  This is a stable state, you can easily verify that Q = 0 NOR 1 and Q' = 0 NOR 0.

• Now, the external input S is raised by some other circuit.

  R = 0, S = 1, Q = 0, Q' = 1
  

• This is an instable state, the equation Q' = 1 NOR 0 is not satisfied, so that gate will immediately lower the signal Q' to 0:

  R = 0, S = 1, Q = 0, Q' = 0
  

• This is still an instable state, the equation Q = 0 NOR 0 is not satisfied, so that gate will immediately raise the signal Q to 1:

  R = 0, S = 1, Q = 1, Q' = 0
  

  Now, both equations Q = 0 NOR 0 and Q' = 1 NOR 1 are satisfied again, and the state of the latch is stable.

• Finally, the external source of S can be lowered again:

  R = 0, S = 0, Q = 1, Q' = 0
  

  Still the two equations Q = 0 NOR 0 and Q' = 0 NOR 1 are satisfied, the state remains stable, and the latch has stored the new value Q = 1.

This all happens within a fraction of a nanosecond (well, the precise speed depends on the chip technology that is used), but it happens precisely in that order, no matter how fast or slow the components are. The only requirement is, that the R/S signals remain raised long enough for the process to complete. If that is the case, the next state is clearly determined in each state.