VHDL/PlanAhead Error: <countr> remains a black-box since it has no binding entity

Question

How can this error be fixed? PlanAhead 14.7 is able to synthesize but not simulate correctly for this simple counter. The instance "dut : countr port map" remains with a red question mark in the sources tab. I've made sure that all signals are instantiated correctly;tried re-adding sources;tried creating a new project. Working with IP cores can generate this problem apparently but I don't think I am.

Design source:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity countr is
Port (clk : in std_logic;
      reset : in std_logic;
      output: out std_logic_vector(4 downto 0)
 );
end countr;

architecture Behavioral of countr is
signal count : std_logic_vector(4 downto 0);
BEGIN

proc_1: process(clk, reset)
begin
    if reset = '1' then
        count <= (others => '0');
    elsif rising_edge(clk) then
        count <= std_logic_vector(unsigned(count) + 1);
    end if;
end process;
output <= count;
END Behavioral;

Simulation source:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cntr_TB is end cntr_TB;
architecture Behavioral of cntr_TB is
component countr is
port(clk  : in std_logic;
    reset : in std_logic;
    output: out std_logic_vector(4 downto 0)
 );
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal output : std_logic_vector(4 downto 0) := "00000";
signal endOfSim : boolean := false;      
constant period : time := 20 ns;
BEGIN
dut: countr port map (clk => clk, reset => reset, output => output);
clkStimulus: process(clk)
begin
    if endOfSim = false then
        clk <= not clk after period/2;
    end if;
end process;
stim: process
begin
wait for 40 ns;
reset <= '0';
wait;
end process;
END Behavioral;

Answer 1

I deleted and re-added design & simulation sources, which still left the black-box. I opened a new project and added the sources before the project was created and the simulation ran without a problem.