When to use the tick(') for Verilog array initialization?

Question

Array initialization can be done with or without the ':

int a[8] = '{0,1,2,3,4,5,6,7}; // Packed
int b[8] = {0,1,2,3,4,5,6,7};  // Unpacked

Is there a correct way, assuming the array uses an un-packable type like int, string, etc.? Both ways seem to work just fine.

Full code example on EDA Playground: http://www.edaplayground.com/x/3Tc

Answer 1

Based on IEEE 1800-2009:

Array assignment patterns (1) have the advantage that they can be used to create assignment pattern expressions of selfdetermined type by prefixing the pattern with a type name. Furthermore, items in an assignment pattern can be replicated using syntax such as '{ n{element} }, and can be defaulted using the default: syntax. However, every element item in an array assignment pattern must be of the same type as the element type of the target array. By contrast, unpacked array concatenations (2) forbid replication, defaulting and explicit typing, but they offer the additional flexibility of composing an array value from an arbitrary mix of elements and arrays.

So:

int A3[1:3];
int A9[1:9];

A3 = '{1, 2, 3}; #legal
A9 = '{3{A3}};   #illegal
A9 = {A3, 4, 5, A3, 6}; #legal
A9 = '{9{1}}; #legal
A9 = {9{1}}; #illegal

Answer 2

In simple cases as you have shown there is overlap in functionality between assignment patterns and unpacked array concatenation. In fact in very early versions of SystemVerilog, they used the exact same syntax (without the '), but assignment context typing rules proved too complex to use the exact same syntax, so the ' prefix was added to distinguish the two.