Why is my VHDL detector not recognizing the state change?

Question

I am having problem with my VHDL code, I hope someone could help. See, the 'q' signal is supposed to detect whether the state has changed or not, but it never does. It is as if the state never gets from 'detecting' to 'idle'. The q signal remains on the '0' value, even though the state changes, while the reset is off and clk signal is on the upper edge. I hope you get to see where the problem is. P.S. state_reg signal is for state at the moment and the next one is for the next state. qlevel_detected is the signal I used for debugging.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity detector is
    port
    (
            clk, reset :            in std_logic;
            level :                 in std_logic;
            q :                     out std_logic;
            qlevel_detected :       out std_logic
    );
    end detector;

    architecture behavioral of detector is
    type state is (idle, detecting);
    signal state_reg, state_next : state;
    signal level_detected_reg, level_detected_next : std_logic;
    begin
    process(clk, reset)
    begin
            if (reset = '1') then
                    state_reg <= idle;
            elsif (clk'event and clk = '1') then
                    state_reg <= state_next;
                    level_detected_reg <= level_detected_next;
            end if;
    end process;

    process(state_reg)
    begin
            state_next <= state_reg;
            level_detected_next <= level_detected_reg;

    case state_reg is
            when idle =>
                    level_detected_next <= level;
                    state_next <= detecting;

            when detecting =>
                    if (level /= level_detected_reg) then
                            state_next <= idle;
                    end if;
    end case;
    end process;

    -- Output logic
    q <=    '0' when state_reg = idle else
            '1' when state_reg = detecting;

    qlevel_detected <= level_detected_reg;
    end behavioral; 

Answer 1

Your next state process is only sensitive to state_reg. As a combinational process it needs all of its inputs listed in the sensitivity list (or all with VHDL-2008).

process(state_reg, level, level_detected_reg)
begin
...

You are also missing an unconditional else on the assignment to q which will create a latch in synthesis.