VHDL - using two components in a third entity

Question

im pretty new in VHDL, and I have a simple question. I have a MAC (Multiply-And-Accumulate) entity which has 2 components in it: 'multiplier' and 'add_sub_n'. i want the MAC to get two inputs a,b, multiply them and add them to an older result when I used the Mac before. here is my code:

    -- libraries decleration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MAC is 

    port  (a   : in  std_logic_vector(N-1 downto 0);
           b   : in  std_logic_vector(N-1 downto 0);
           mac : in  std_logic_vector(N-1 downto 0);
                 s   : out std_logic_vector(N-1 downto 0);
end MAC;

architecture MAC_Logic of MAC is

component Multiplier is 
    port(
    a,b : in  std_logic_vector(N-1 downto 0);   
    c   : out std_logic_vector(N-1 downto 0)); 
end component;

component Add_Sub_N is
    port(
    a,b  : in  std_logic_vector(N-1 downto 0);
    sub  : in std_logic;
  cout : out std_logic;
    s    : out std_logic_vector(N-1 downto 0));
end component;

signal temp1 : std_logic;

    begin   
    mul : Multiplier
        port map(a=>a, b=>b, c=>temp1);

  addsub : Add_Sub_N
        port map(a=>temp1, b=>mac, sub=>0, cout=>cout, s=>s); 

    end MAC_Logic;

Im pretty stuck. if someone can please help I would appreciate it. thanks!

Answer 1

You have the following operations to perform:

m = a * b
acc' = m + acc
acc = acc'

Where acc' is the new value to store in the accumulator. Your code has entities for the multiply and add but nothing to describe the register that implements the accumulator. The accumulator register provides the second input to the adder. A control input will also be needed to enable writing to the accumulator only when a new product is available.