How to make an LED blink in Verilog?

Question

I have a FPGA board and I'm trying to make an led blink with a 30% timing margin of 60 seconds.

I have the clock set at 24 MHz

Here is the code I used from a tutorial website

reg [33:0] counter;
reg state;

assign ledg[0] = state;

always @ (posedge clock) begin
    counter <= counter + 1;
    state <= counter[24]; //
end

There are 3 concerns I have about this code:

1. I don't understand why the counter was declared with the subscript [33:0]

2. I don't understand why the state is set to unblock when counter[24]

3. Upon using this code, my timing margin is off, i.e. when I timed the amount of blinks per 60 seconds, it was 0.73, which is off by .03 according to the requirements.

Thanks

Answer 1

I don't understand why the counter was declared with the subscript [33:0]

The subscript [33:0] means that your counter has 34 bits. This means it can count from 0 to 2^(34)-1, or 0 to 17179869183 in decimal.

I don't understand why the state is set to unblock when counter[24] Upon using this code, my timing margin is off, i.e. when I timed the amount of blinks per 60 seconds, it was 0.73, which is off by .03 according to the requirements.

state is assigned to the 24th bit of the counter. That means that whenever the 24th bit of the counter is equal to 1, the state will be '1' and the LED will turn on. Whenever the 24th bit of the counter is 0, the state will be 0 and the LED will turn off.

Note that the 24th bit of the counter toggles every 2^24 cycles, or 16,777,216 cycles. Remember that your clock is 24 MHz so that means the clock toggles 24,000,000 times per second. So if your LED state toggles every 16,777,216 cycles, that means it toggles (16,777,216/24,000,000) times per second or every 0.699 second - so it should be very close to the 0.7 that you are looking for.

Answer 2

//300MHz to 1Hz

module top( input clk, input reset, output led );

reg [27:0] counter;
reg led;
reg clkout;

always @(posedge clk) begin
    if (counter == 0) begin
        counter <= 149999999;
        clkout <= ~clkout;
    end else begin
        counter <= counter - 1;
    end
end

always @(posedge clkout) begin
        if (reset == 0) begin
            led <= 0;
        end else begin
            led <= ~led;
        end
    end