Verilog: Better syntax for many cases in a case structure

Question

I have a case structure in Verilog with approximately 95 cases.

        case(address)
            5'd0: header_buffer[7:0] <= writedata;
            5'd1: header_buffer[15:8] <= writedata;
            5'd2: header_buffer[23:16] <= writedata;
            5'd3: header_buffer[31:24] <= writedata;

As you can see, there is a very predictable pattern. Is there a better way to write this so that I don't have to manually write out all of the cases and so that I can scale it to an arbitrarily large size such as 100 or 200 cases? It seems like some type of for loop syntax would be very useful.

Answer 1

It can be done in one or two lines with bit slicing, however you need to check if your synthesizer property generates it.

header_buffer[8*address +: 8] <= writedata;

If the address could go out of range (ex address==100 and max is 95) then you should use if condition:

if (address < MAX_ADDRESS)
  header_buffer[8*address +: 8] <= writedata;

Description and examples can be found in IEEE Std 1800-2012 § 11.5.1 Vector bit-select and part-select addressing. First IEEE appearance is IEEE 1364-2001 (Verilog) § 4.2.1 Vector bit-select and part-select addressing. You may also want to check out a previously answered question on Indexing vectors and arrays with +:

Word of caution. Despite the fact that bit slicing has been part of the standard since Verilog-2001, not all tools have fully implemented bit slicing with proper optimization. Some times a traditional full case statement will generate better results even though the two are functionally identical.