Makefile: Error referencing source files in "src" directory

Question

[edit]- The answer is I have incorrectly defined the path to the include directory. Embarrasing mistake.

I am writing a makefile that builds objects from .c files in a src directory with headers in an include directory and stores them in an obj directory, and then builds and exe from those objects. A toy version is below.

# Makefile

IDIR = ../include
CC = gcc
CFLAGS = -I$(IDIR) -Wall

SDIR = src
ODIR = obj

_SOURCES = main.c aux1.c aux2.c aux3.c
SOURCES = $(patsubst %,$(SDIR)/%,$(_SOURCES))

_OBJECTS = $(_SOURCES:.c=.o)
OBJECTS = $(patsubst %,$(ODIR)/%,$(_OBJECTS))

_DEPS = aux1.h aux2.h aux3.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

EXE = exefile

$(ODIR)/%.o: $(SDIR)/%.c $(DEPS)
        $(CC) -c -o $@ $< $(CFLAGS)

$(EXE): $(OBJECTS)
        $(CC) -o $@ $^ $(CFLAGS) 

.PHONY: clean

clean:
        rm *o $(EXE)

The directory the makefile is in looks like this (when you ls)

include  Makefile  obj  src  trash

When I type make, I get the following error

make: *** No rule to make target `obj/main.o', needed by `exefile'.  Stop.

I suspect the problem is with this line

$(ODIR)/%.o: $(SDIR)/%.c $(DEPS)

I am attempting to build each object file in obj/ by referencing the corresponding source file in src/ but the line seems do to something else. Is this the case? Is there an easy way to reference .c files in the source directory without "entering" the directory?

Thanks in advance

Answer 1

I believe your problem is the $(DEPS) dependency.

You set IDIR to ../include but from the toplevel directory (where make is run from) that path is incorrect.