Signals and synthesis of registers/flip flops in VHDL

Question

Waveform link included I have a confusion regarding the value assignment to signal in VHDL.

Confusion is that I have read that values to signal gets assigned at end of process.

1. Does the value get assigned right when the process finishes or when the process is triggered the next time?

2. If it is assigned at the end of the process then consider this scenario (3 flip flops in series i.e output of one flip flop is input to another) then if D1 is 1 at time 0 will not the output Q3 be 1 at the same time?

Answer 1

(1) Right when the process finishes. More precisely, right after this and ALL processes running alongside this process have finished, and before any processes are subsequently started. So when any signal assignment happens, no process is running.

(2) Q3 will become the value on D1 three clock cycles earlier. Whether that value was '1' or not I can't tell from your question!

Answer 2

The signal assignment is done only at the end of the process. After signal assignment, there may exist signal updates and because of the signal updates, the process itself or maybe other processes which are sensitive to some of the updated signals will be triggered. This is the concept of delta-cycle. It happens in a zero simulation time. signal updates -> triggers process->at the end of the process, signals are updated ----------------------------------- ----------------------------------- this is one delta cycle starting of the second delta cycle

when there will be no signal update, the process finishes and the the simulation time increments.