How can I assign something to nothing in Verilog?

Question

For example, I have something like this:

reg b5,b3,b2,b0;
wire [5:0] vector;

assign {b5,<unused>,b3,b2,<unused>,b0} = vector;

I don't care about bits 1 and 4 of vector.

What is the best thing to use instead of ? 1'bZ? 1'b0? or 1'bX? Or...?

Answer 1

How about:

reg b5,b3,b2,b0;
wire [5:0] vector;
reg dummy1, dummy2;

assign {b5,dummy1,b3,b2,dummy2,b0} = vector;

Answer 2

You can assign only the bits that you actually do care about.

assign b5 = vector[5];
assign b3 = vector[3];
assign b2 = vector[2];
assign b0 = vector[0];

You can also do this with subsets of the vector:

reg [1:0] 2bits;
wire [5:0] vector;
assign 2bits = vector[1:0];