Trouble having port mapping two modules in one

Question

This is a control unit for my 16 bit MIPS, I am trying to connect the alucontrol to the alu unit opcode but since it was an output and alu unit op a input i used a signal opsignal, the code gives no syntax error but shows this warning i have mentioned below.

I am a newbie and I don't know how to connect my aluunit to control unit even if I am actually connecting it. Also if I am not using funct, A and B so it will run with the same logic, right? I mentioned these inputs and outputs in my port map but it showed error as they were open ports. Using 'open' did not fix the problem so I just removed them, does it affect my code? There are so many warnings. I just don't know how to resolve them

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity controlunit is 
  Port ( opcode : in  STD_LOGIC_VECTOR (2 downto 0);
         --zero : in  STD_LOGIC;
         w_en : out  STD_LOGIC;
         regdst : out  STD_LOGIC;
         alusrc : out  STD_LOGIC;
         --branch : out  STD_LOGIC;
         memwrite : out  STD_LOGIC;
         memtoreg : out  STD_LOGIC;
         alucontrol : out  STD_LOGIC_VECTOR (1 downto 0);
         pcsrc : out  STD_LOGIC);
end controlunit;

architecture Behavioral of controlunit is

  component maindecoder is
    Port ( opcode : in  STD_LOGIC_VECTOR (2 downto 0);
           w_en : out  STD_LOGIC;
           regdst : out  STD_LOGIC;
           alusrc : out  STD_LOGIC;
           branch : out  STD_LOGIC;
           memwrite : out  STD_LOGIC;
           memtoreg : out  STD_LOGIC
           --aluop : out  STD_LOGIC_VECTOR (1 downto 0)
         );
  end component;

  component alu is
    Port ( --clk: in STD_LOGIC;
           --A : in  STD_LOGIC_VECTOR (15 downto 0);
           --B : in  STD_LOGIC_VECTOR (15 downto 0);
           --funct: in STD_LOGIC;
           op: in STD_LOGIC_VECTOR (1 downto 0);
           zero  : out std_logic;
           Result : out  STD_LOGIC_VECTOR (15 downto 0));    
  end component;

  --signal alusig: STD_LOGIC_VECTOR (1 downto 0);
  signal opsignal: STD_LOGIC_VECTOR (1 downto 0);
  signal branch: STD_LOGIC;
  signal zero: STD_logic;

begin

  -- instantiate maindecoder
  decoder: maindecoder port map (opcode => opcode, w_en => w_en,
           regdst => regdst, alusrc => alusrc, branch => branch, memwrite => memwrite, memtoreg => memtoreg);

  aluunit: alu port map (op => opsignal, zero => zero);

  alucontrol <= opsignal;

  pcsrc <= branch and zero;

end Behavioral;


WARNING:Xst:753 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 46: Unconnected output port 'aluop' of component 'maindecoder'.
WARNING:Xst:753 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected output port 'Result' of component 'alu'.
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'clk' of component 'alu' is tied to default value.
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'A' of component 'alu' is tied to default value.
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'B' of component 'alu' is tied to default value. 
WARNING:Xst:752 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected input port 'funct' of component 'alu' is tied to default value.
WARNING:Xst:653 - Signal <opsignal> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:1290 - Hierarchical block <aluunit> is unconnected in block <controlunit>. It will be removed from the design.

Code for alu:

   library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.std_logic_unsigned.all;
   use ieee.std_logic_arith.all;

  entity alu is 
  Port ( clk: in STD_LOGIC;
          A : in  STD_LOGIC_VECTOR (15 downto 0);
       B : in  STD_LOGIC_VECTOR (15 downto 0);
          funct: in STD_LOGIC;
          op: in STD_LOGIC_VECTOR (1 downto 0);
          zero  : out std_logic;
       Result : out  STD_LOGIC_VECTOR (15 downto 0));

  end alu;

  architecture Behavioral of alu is
begin
 process (clk, op, funct, A, B)
 begin
  if (clk'event and clk = '1') then
    case op is
        when "00" => Result <= A+B;
        when "01" => Result <= A-B;
        when "10" => case funct is 
                        when '0' => Result <= A+B;
                        when '1' => Result <= A-B;
                        when others => null;
                        end case;
        when others => null;
    end case;
    end if;
end process;
    process (A,B) begin
        if (A = B) then
        zero <= '1';
        else zero <= '0';
        end if;
    end process;
   end;

Code for maindecoder

   ibrary IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.NUMERIC_STD.ALL;

   entity maindecoder is
   Port ( opcode : in  STD_LOGIC_VECTOR (2 downto 0);
       w_en : out  STD_LOGIC;
       regdst : out  STD_LOGIC;
       alusrc : out  STD_LOGIC;
       branch : out  STD_LOGIC;
       memwrite : out  STD_LOGIC;
       memtoreg : out  STD_LOGIC;
       aluop : out  STD_LOGIC_VECTOR (1 downto 0));
  end maindecoder;

  architecture Behavioral of maindecoder is
  signal control: std_logic_vector (7 downto 0);
  begin
    process (opcode)
begin
    case opcode is
        when "000" => control <= "11000010"; -- R-type
        when "001" => control <= "10100100"; --lw
        when "010" => control <= "00101000"; --sw
        when "011" => control <= "00010001";--beq
        when others => control<= "--------";        --illegal opcode
    end case;
end process;

w_en    <= control(7);
regdst  <= control(6);
alusrc  <= control(5);
branch  <= control(4);
memwrite <= control(3);
memtoreg <= control(2);
aluop       <= control(1 downto 0);

   end Behavioral;

Answer 1

WARNING:Xst:753 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 46: Unconnected output port 'aluop' of component 'maindecoder'.

The problem here is exactly what it says (you left an output unconnected, which isn't an error), but it's related to a more critical error further on:

WARNING:Xst:653 - Signal <opsignal> is used but never assigned. This sourceless signal will be automatically connected to value 00.

You probably meant to map opsignal to the aluop output on maindecoder.

WARNING:Xst:753 - "E:/Xilinx Projects/controlunit/controlunit.vhd" line 49: Unconnected output port 'Result' of component 'alu'.

Again, exactly what it says. Are you sure you don't want to connect Result?

The rest of the errors indicate you have some other fairly serious problems, namely, you've left a bunch of inputs unconnected - you've commented out a bunch of ports on your component declaration for alu and not mapped them. Why? Note that these ports are fairly critical to the operation of alu - without at least some of them, it won't actually do anything.

(edit)

Re: your comment "I used a signal because I cannot map an output to an input.":

op is an input to alu because alu "reads" it, in a manner of speaking. alu does not generate that value or drive that port - it has to come from somewhere else, possibly outside the code you've posted here. Therefore, trying to obtain its value from alu is meaningless. You need to determine what the source of that control is. If it's maindecoder, then you can compose it from that component's outputs, but I'm not sure if that's what you need.