The answer will depend on your target platform, for example you may have P1020RDB, or something else.
Assuming that SDRAM ECC can be enabled on the platform (this may include extra RAM to hold syndrome bits, e.g. 36-bit data path) then ECC needs to be enabled at the time that SDRAM controller is initialized. It can't be turned on at runtime while the SDRAM is already in use. Thorough study of chip reference manual, target platform documentation, and (ideally) target BSP u-boot source will reveal everything that's needed.