random number array in Verilog

Question

I want to test all possible combinations of inputs to a verilog module. I have been able to do generate these inputs by building an array with a nested for loop. However I want to go through the array in random order. How can this be done, or is there a way to generate an array of all possible inputs that is already in random order?

Answer 1

If you want to rearrange a list of test cases like shuffling a deck of cards, there's an algorithm called the Fisher–Yates shuffle to do that. Or if you're using SystemVerilog, toolic pointed out that there's a built-in shuffle method for arrays.