Can I create a const object in SystemVerilog?

Question

I'd like to create a const object inside my SystemVerilog class. Does SystemVerilog support const objects (and how?), or does it only support const primitive types.

I'd like to do something like:

const my_object MY_CONST;

const begin
    MY_CONST = new();
    MY_CONST.param1 = "value1";
    MY_CONST.param2 = "value2";
end

Answer 1

You can create constant class instances.

An instance of a class (an object handle) can also be declared with the const keyword.

const class_name object = new(5,3);

In other words, the object acts like a variable that cannot be written. The arguments to the new method shall be constant expressions (see 11.2.1). The members of the object can be written (except for those members that are declared const).

Answer 2

I would have liked to comment on Adam12's answer, but I can't so I'll post a new answer instead, sigh!

In SV MY_CONST would only be a constant handle. So probably you can't assign another object to the handle, but the contents of the object being pointed to by the handle can still be modified.

I haven't heard of any const begin ... end construct. I would think that there is a restriction on calling new — it should be called at the time of assigning to the const handle, or new can be called in the constructor if the const handle is a member of a class. The member functions of the const handle could be called anywhere, I would guess.