VHDL calculation, different but still the same

Question

Hard to explain the problem in the title, so please read on.

I have a project where we are implementing a sobel filter. At first, the image didn't work as it should do, with the sobel calculations

Gx <= ("000" & p3-p1)+(("00" & p6 & '0')-("00" & p4 & '0'))+("000" & p9-p7);
Gy <= ("000" & p7-p1)+(("00" & p8 & '0')-("00" & p2 & '0'))+("000" & p9-p3);

but with the same calulation expressed in a different way

Gx <= ("000" & p3)+("00" & p6 & '0')+("000" & p9)-("000" & p1)-("00" & p4 & '0')-("000"
 & p7);
Gy <= ("000" & p7)+("00" & p8 & '0')+("000" & p9)-("000" & p1)-("00" & p2 & '0')-("000"
 & p3);

it worked perfectly. Still, the simulations of the filter alone is exactly the same. Has it something to do with how I pad the zeroes before the vectors?

Answer 1

Without knowing the data types I'm not completely sure if this is the cause, but my guess would be that if p1 > p3 (and some of the other ones too) you'll get different results from the two types of calculations. Pseudo-code example:

p1 = "010";
p3 = "001";

--Method1:
res = "000" & p3-p1 = "000" & "111" = "000111";


--Method2
res = ("000" & p3) - ("000" & p1) = "000001" - "000010" = "111111";