Verilog: Pass a vector as a port to a module

Question

I have two modules

1. counter: Output is a vector called error_count.
2. lcd: Module to display the code on an LCD. Input includes clock and error_count.

Following snippet of the code is most relevant and attached below:

1. Top level module:

   counter counter1 (..., error_count);
   lcd lcd1 (..., error_count);

2. counter module:

   module counter (..., error_count);
   ...
   output reg [31:0] error_count = 0;
   ... //Update counter every clock cycle
   endmodule
   

3. lcd module:

   module lcd (..., error_count);
   ...
   input [31:0] error_count;
   ... //error_count used to display on LCD
   endmodule
   

What is wrong with this code? The display just prints 0 as the output. Is there anything wrong with the way I am passing the the vector?

Additional Info: I am using the Xilinx Spartan 3E starter kit for testing this code. The LCD code is fine and I have tested it with local counter (which was reg[31:0]).

Answer 1

You need to declare 32-bit wire within the top-level module to connect the two ports.

wire [31:0] error_count;

If you leave this out, an implicit net is declared which is only a 1-bit wire and will not connect the vectors properly.

This mistake is a classic Verilog gotcha. The presentation here has a good explanation of this one and others:

http://www.sutherland-hdl.com/papers/2006-SNUG-Boston_standard_gotchas_presentation.pdf