Syntax of the full hierarchical names used in Xilinx UCF files

Question

I'm trying to create a TIG constraint in the UCF file of my project.
Problem is, I just can't get the hierarchical name right.
The structure I'm dealing with is the following (pseudo-code showing the hierarchical position of the signal that needs to be addressed):

m1: module1  
    g1: for i in 0 to m generate  
        g2: if x /= 0 generate  
            m2: module2  
                reset : in std_logic;

Among others I tried NET "m1/m2/reset" TIG; , NET "m1/g1.g2.m2/reset" TIG; and NET "m1/g1*.g2.m2/reset" TIG; (the last one was inspired from one of the intermediate files produced during synthesis *.xdl).
What is the correct way to address the reset net within m2? I looked at the Xilinx Constraint Guide but found no detailed explanation on this.

Answer 1

A recent XST User Guide might have a section on XST Naming Conventions with subsections on *XST Net Naming Conventions, XST Instance Naming Conventions and XST Name Generation Control. The last telling how to control name generation in the netlist (hierarchy separator, bus delimiter, case, duplication suffix, viewable in Synthesis Properties). Your third example above looks promising. You can get closer to the netlist by viewing schematics or the constraint editor. Can you add TIG to the reset in m1? (it's forward referential).