System Verilog interface with different inputs

Question

I have defined an interface for my DUT as such:

interface video_input_interface(clk, rst);

   input logic       clk;
   input logic       rst;
         logic[1:0]  x_lsb;
         logic[1:0]  x_msb;
         logic[3:0]  x;

   assign x = {x_msb, x_lsb};
endinterface

The reason I did this is because my DUT has separate ports for x_msb and x_lsb and I want to explicitly show which bits of signal x I am connecting to these ports. For example, when instantiating the DUT:

interface video_input_interface vif;
dut udut(
    .msb(vif.x_msb),
    .lsb(vif.x_lsb),
.............
);

Now the issue is I have 2 drivers in my agent:

Driver A: When driving the interface from Driver A, I would like to drive signal x and not x_lsb, x_msb.

Driver B: When driving the interface from Driver B, I would like to drive signal x_lsb and x_msb individually.

I would think that my solution would split up signal x in my interface into x_lsb and x_msb. In DriverA, I can just drive this signal x. Also, for driver B the interface would be ok with me accessing the bits individually and everything would work just fine... not!

The assign causes signal x to be "X - unknown value". I have to drive x_msb and x_lsb individually for DriverA. Or other option is to

assign x_lsb = x[1:0]
assign x_msb = x[3:2]

This means DriverA would work, but would run into same problem from DriverB (when trying to drive x_lsb and x_msb).

Is there a solution to this? Thanks

Answer 1

You can use clocking blocks, one per driver:

interface video_input_interface(clk, rst);

   input logic       clk;
   input logic       rst;
         logic[1:0]  x_lsb;
         logic[1:0]  x_msb;

  clocking cb_a @(posedge clk);
    output x = { x_lsb, x_msb };
  endclocking

  clocking cb_b @(posedge clk);
    output x_lsb;
    output x_msb;
  endclocking

endinterface

From driver A, you would always reference cb_a:

@(posedge clk);
video_if.cb_a.x <= 'hA;

From driver B, you would always reference cb_b:

@(posedge clk);
video_if.cb_b.x_msb <= 'h1;
video_if.cb_b.x_lsb <= 'h2;

Full example on EDAPlayground: http://www.edaplayground.com/x/3hK

You just have to be careful not to drive from both drivers at the same time. Read more on clocking blocks in Section 14. Clocking blocks of the SV 2012 standard.

Answer 2

Your question is a bit unclear... So do drivers A and B drive x simultaneously? What should be the value of x when x_msb and x_lsb are driven by B and x is driven by A?

You already assign to x in the interface. Therefore, you cannot drive it in another module (Driver A) because x cannot have multiple drivers.

If the two drivers are not driving simultaneously, how about a multiplexed solution as in the following?

interface video_input_interface(clk, rst);

   input logic       clk;
   input logic       rst;
         logic[1:0]  x_lsb;
         logic[1:0]  x_msb;
         logic[3:0]  x;
         logic       driverIsA;       //Indicates the driver is A
         logic       xValueFromA;     //The x value driven by A

   assign x = driverIsA ? xValueFromA : {x_msb, x_lsb};
endinterface