Port declarations without direction verilog
-
21-12-2019 - |
Question
So this is 1/4 of the files or behavioral model I have but I keep getting this error in the file. Am I doing this correctly in verilog? I'm getting a:
"Port declarations without direction are only supported in System Verilog. You must compile with the -sverilog flag to enable support for this feature."
module NSG_function
(
input x, [1:0] q, // current_state,
output [1:0] d // next_state
);
assign d[1] = ~x&q[0]&q[1] | x&~q[0]&q[1] | x&q[0]&~q[1];
assign d[0] = ~x | ~q[0]&q[1];
endmodule
Solution
Your problem is with the input q
.
Though you put it on the same line as input x,
, since you declare q as an array, it needs its own input declaration.
module NSG_function
(
input x,
input [1:0] q, // current_state
output [1:0] d // next_state
);
assign d[1] = ~x&q[0]&q[1] | x&~q[0]&q[1] | x&q[0]&~q[1];
assign d[0] = ~x | ~q[0]&q[1];
endmodule
OTHER TIPS
You probably need to specify input
for each signal:
input x,
input [1:0] q, // current_state,
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