Case statement returning incorrect value

Question

I am trying to do this 7segment display function. The input "rn" is the number i want to display, but while I do the simulation on ISE suite, it just can recognize the "rn"'s when it is equal to 0 or 1. Any value greater than that will fail, so the output seg[7:0] will be just 8 bits of 0.

module LED_7seg(clk, btn, rn, segA, segB, segC, segD, segE, segF, segG, segDP, anodes);

input clk, btn;       
input [4:0] rn;
output [3:0] anodes;     

output segA, segB, segC, segD, segE, segF, segG, segDP;

wire [4:0] rn_in;
reg [7:0] seg;


assign {rn_in[4], rn_in[3], rn_in[2], rn_in[1], rn_in[0]} = rn;


always @ (*)
case (rn_in)
    (5'b00001 || 5'b10001) : seg = 8'b11111100;    //0
    (5'b00001 || 5'b10001) : seg = 8'b01100000;     //1
    (5'b00010 || 5'b10010) : seg = 8'b11011010;     //2
    (5'b00011 || 5'b10011) : seg = 8'b11110010;     //3
    (5'b00100 || 5'b10100) : seg = 8'b01100110;     //4
    (5'b00101 || 5'b10101) : seg = 8'b10110110;     //5
    (5'b00110 || 5'b10110) : seg = 8'b10111110;     //6
    (5'b00111 || 5'b10111) : seg = 8'b11100000;     //7
    (5'b01000 || 5'b11000) : seg = 8'b11111110;     //8
    (5'b01001 || 5'b11001) : seg = 8'b11110110;     //9
    (5'b01010 || 5'b11010) : seg = 8'b11101110;     //10
    (5'b01011 || 5'b11011) : seg = 8'b00111110;      //11
    (5'b01100 || 5'b11100) : seg = 8'b10011100;     //12
    (5'b01101 || 5'b11101) : seg = 8'b01111010;     //13
    (5'b01110 || 5'b11110) : seg = 8'b10011110;     //14
    (5'b01111 || 5'b11111) : seg = 8'b10001110;     //15
    default : seg = 8'b00000000; 
endcase

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = seg;

endmodule

Any assistance will be helpful.

Answer 1

You are using || operator, which is logical or. In your code, you are calculating logical OR of two non-zero values, which always evaluates to 1. For example: (5'b00001 || 5'b10001) = 1.

I think what you want is the following:

Change (for each case item)

(5'b00001 || 5'b10001) : seg = 8'b11111100;    //0

into:

5'b00001, 5'b10001 : seg = 8'b11111100;    //0

The former means if rn_in is equal to (5'b00001 || 5'b10001)=1. The latter means if rn_in is equal to 5'b00001 or rn_in is equal to 5'b10001.