Is it possible to create SystemVerilog wrappers with modports for Verilog modules?
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26-12-2019 - |
Question
Is it possible to create SystemVerilog wrappers with modports?
Let's say I have an interface:
interface axi_if(input clk, input rst);
logic arlen;
clocking mclk@(posedge clk);
output arlen;
endclocking
modport Master(clocking mclk, input clk, input rst);
endinterface
In the DUT wrapper I have:
axi_if my_if(clk, rst)
my_dut you_dut(.arlen(my_if.Master.mclk.arlen));
I tried doing this but I got a cross-module reference error. Any suggestions/clues what is wrong?
Solution
There are two separate problems here.
- A Modport is not a scope and you do not use it when accessing interface members through hierarchical references as if it were a module instance. You only use modport when connecting interface ports or virtual interface to limit access through the port. If your my_dut had an interface port, you could write
my_dut you_dut(.a_if(my_if.Master));
to specify that my_dut only has access to the interface signals specified by Master. - You didn't show if the my_dut arlen port is an input or and output, but it can't be an output port. That because the only thing you can do with
mclk.arlen
is drive it with a synchronous drive statement:mclk.arlen <- expression;
. You cannot read it. So if arlen is an input port, you probably want to writemy_dut you_dut(.arlen(my_if.arlen));
.
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