Can Make undefine a variable?

Question

I'm working in an embedded system (RTXC) where I need to disable the debugger functionality which is enabled through a #define command. However, when I change the #define to undefine, compilation goes off fine, but when the linker runs, it encounters an error about a symbol not existing that belongs to the debug code (which should have been taken care of by the debugger variable not being defined). Is there any way for Make to ensure that a preprocessor variable does not get defined or stays undefined ?

Answer 1

The answer to your question is no, Make can't absolutely prevent a variable from being defined by, say, a #define expression in the code.

You seem to have an elusive problem. It could be a bug in your Makefiles, a misspelled directive, a bad macro (if you'll pardon the tautology) or something trivial. I'd suggest burning the forest: cut out everything until the problem stops, then see where it was hiding. If you get down to HelloWorld and the problem persists, let us know.

Answer 2

No. You will need to fix the bug in your code.

More specifically, there is something that is referencing the debug side of things outside of an #ifdef. Make won't be able to help you there.

Another possibility is that you have a .o or something left over from a previous build; you might want to try cleaning the build tree.