Can't infer register in Quartus II (VHDL)

Question

This is the full code

library ieee;
use ieee.std_logic_1164.all;

entity move_key_detector is
    PORT(
        clk : IN STD_LOGIC;
        done : IN STD_LOGIC;
        hex : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        up, down : out std_logic
    );
END move_key_detector;

architecture arch of move_key_detector is

    type statetype is (IDLE, RECEIVED_BREAK);
    signal next_state, current_state : statetype :=IDLE;

begin

process (Clk) begin
    if(rising_edge(Clk)) then
        current_state <= next_state;
    end if;
end process;


process(done) begin
next_state <= current_state;
    case current_state is
        when IDLE=>
            if(done = '1') then
                if (hex = "00011101") then up <= '1';
                elsif(hex = "00011011") then down <= '1';
                --check to see if a break code is sent
                elsif (hex = "11110000") then next_state <= RECEIVED_BREAK; 
                end if;
            end if;
        when RECEIVED_BREAK=>
            if(done ='1') then
                if (hex = "00011101") then up <= '0';
                elsif(hex="00011011") then down <= '0';
                end if;
                next_state <= IDLE;
            end if;
        end case;
end process;

The errors are:

Error (10821): HDL error at move_key_detector.vhd(31): can't infer register for "down" because its behavior does not match any supported register model

Info (10041): Inferred latch for "down" at move_key_detector.vhd(29)

Error (10821): HDL error at move_key_detector.vhd(31): can't infer register for "up" because its behavior does not match any supported register model

Info (10041): Inferred latch for "up" at move_key_detector.vhd(29)

Error (10818): Can't infer register for "next_state" at move_key_detector.vhd(41) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "next_state" at move_key_detector.vhd(33) because it does not hold its value outside the clock edge

I have been getting this kind of errors. I followed this recommendation, reading the HDL Manual,and I still don't know how to fix this.

Can anyone help me? Thank you very much!

Answer 1

Why do you have a second process? It looks like it contains what is intended to be asynchronous code.

If you need the process so you can use if and case constructs, you need to put anything that can affect the desired output into the process sensitivity list (ie: done AND current_state & hex).

You are also potentially assigning next_state two different values, which is generally a bad thing when targeting an FPGA. I suggest moving the "next_state <= current_state" inside the case statement and explicitly assigning all terms in all branches of your case/if statements (I'm guessing a bit at what you're expecting for behavior, but you should get the general idea):

case current_state is
    when IDLE=>
        if(done = '1') then
            if (hex = "00011101") then 
                up <= '1';
                down <= '0';
                next_state <= current_state;
            elsif(hex = "00011011") then 
                up <= '0';
                down <= '1';
                next_state <= current_state;
            --check to see if a break code is sent
            elsif (hex = "11110000") then 
                up <= '0';
                down <= '0';
                next_state <= RECEIVED_BREAK; 
            ...

You could also use a selected signal assignment outside of a process if you are intending to generate asynchronous logic.

If you are really attempting to infer latches for the up/down/next_state signals, you need to be a lot more explicit about what you want to happen, either directly in your code or in your question to us so we can help you.