MIPS floating-point: swc1 vs. s.s
-
19-09-2019 - |
Question
I'm doing some work involving MIPS
assembly, and I keep coming across these four floating-point load/store pseudoinstructions: l.s
, l.d
, s.s
, s.d
. I found some documentation online and figured out that there are four "actual" instructions that seem to do the same thing: lwc1
, ldc1
, swc1
, and sdc1
.
My only question is, what's the difference? As far as I can tell, both sets of instructions do exactly the same thing. Do the pseudos maybe exist just because they're easier to read?
Thanks in advance for any insight.
Solution
My only question is, what's the difference? As far as I can tell, both sets of instructions do exactly the same thing.
Yes, you're right. The only difference that could appear is when a pseudo-instruction is translated to more than one "real" instruction.
Do the pseudos maybe exist just because they're easier to read?
Again, yes. That's why they exist. They give the illusion of a more expressive instruction set. Quoting Computer organization and design / Patterson & Hennessy:
... the assembler can also treat common variations of machine language instructions as if they were instructions in their own right. The hardware need not implement these instructions; however, their appearance in aassembly language simplifies translation and programming. ...
Given your example, it's more "clear" to say:
l.s $f2, 24(t1) # Load Single contained in 24(t1) to $f2
than
lwc1 $f2, 24(t1) # Load Word into Coprocessor 1 from 24(t1) to $f2
as well as you can understand better:
move $7, $18 # move contents of $18 to $7
than
add $7, $18, $0
For me, it's just be helped by mnemonics to get better legible code.
OTHER TIPS
Actually i think,
LWC1 is Load Word to Co-processor 1
LDC1 is Load Double Word to Co-processor 1
etc...
Guess what, I hit on a Patent page trying to remember these.
US Patent 5555384 - Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction
There are two types of load instructions implemented by FPC 20:
LWC1 (Load Word Coprocessor 1, shown in FIG. 4) and
LDC1 (Load Double Word Coprocessor 1, shown in FIG. 8).LWC1 loads a 32-bit word from the memory subsystem into the FPC general registers.
LDC1 loads a 64-bit double word from the memory subsystem into the FPC general registers.
which confirms it.
(btw: don't bother to search for the figures referred here unless you
have access to the site).