Issue with Makefile in top level directory, sources in subdirectories
-
19-09-2019 - |
Question
I have a directory called project
.
It contains two sub-directories called client
and server
, and a makefile called Makefile
.
client
and server
have got source files called client.c
and server.c
, respectively.
I don't have any separate makefiles in the subdirectories for sources belonging to that directory. All builds are done by the single makefile. The Makefile
code is
FLAGS = -W -Wall -g -pthread
SERV =./server/server.c #My server code
CLI =./client/client.c #My client code
build:svr cnt
svr: $(SERV)
cc $(FLAGS) $(SERV) -o ./server/server.out
cnt: $(CLI)
cc $(FLAGS) $(CLI) -o ./client/client.out
Now I ran make cnt
and it replied
cc -W -Wall -g -pthread ./client/client.c -o ./client/client.out
The problem is all the subsequent make cnt
commands end up compiling it again and outputting the above text even though I'm not changing ./client/client.c
I'm stuck here. Don't know what to do.
What I want to do is:
- With
make cnt
, compileclient/client.c
and output its executable in theclient/
directory - With
make svr
, compileserver/server.c
and output its executable inserver/
directory. - And with
make, compile both
server/server.cand
client/client.c` and output their executables in their respective directories
But since I don't have any executables called svr
and `cnt the problem I am having isn't solved.
If I change the target to ./client/client.out
instead of cnt
and then call make client/client.out
then it would be fine, exactly what I need but I don't want to enter long command make client/client.out
in my terminal
The workaround I have got is as follows
cnt: $(CLI)
cc $(FLAGS) $(CLI) -o cnt
cp cnt ./client/client.out
But not quite satisfied with it. I'm sure what I want to do is really simple and there should be some convenient way around doing it. So how can I do that?
Solution
Let's formulate what you want. You want target named `cnt' not to be rebuilt. The makefile you've written knows nothing about client.out file, because it only appears in shell commands within a rule. Make program doesn't read information from shell commands, it only does substitutions there and executes them.
When makefile chooses the targets it will rebuild (`cnt' is one of these targets), it compares update time of a target file with update time of its prerequsites. Since at the time you run ``make cnt'' the file named cnt is absent, the target named so is considered as requiring update. So commands are run and yield no file named cnt, so next make run will consider it for updating as well.
There are two possible solutions. The first one is to give targets same names as of the file, that the rule commands will generate. So, you might end up like this:
client/client.out: $(CLI)
cc $(FLAGS) $(CLI) -o ./client/client.out
Your questioin has nothing to do with directories, by the way. You should also read about .PHONY directive, use $(CC) instead of cc and read gnu make manual, which might be very helpful.
OTHER TIPS
Try this:
SERVO =./server/server.out CLIO =./client/client.out .PHONY: srv cnt build build: svr cnt svr: $(SERVO) cnt: $(CLIO) $(SERVO) $(CLIO): %.out : %.c cc $(FLAGS) $^ -o $@
Now you can make srv, make cnt, or just make.
There are slightly more sophisticated things you can do, but this should be enough for now.