Does “signal” imply δ delay in VHDL?

Question

Hello i was wondering how a signal declaration really works in VHDL. Does it imply delay since its an internal signal? Do signals have an internal memory? example:

Architecture SD_BEH of SD is
signal C: std_logic;
begin
 process (A)
  begin 
   C<=A;
   if (C='1') then B<=A;
   else B<= '0';
   end if;
  end process;
end SD_BEH;

Does this declaration of C introduce δ delay? If so why? Is it a standard in VHDL? Thanks.

Answer 1

Signals only propagate at the end of a delta cycle, so you could call that having "memory" as in some manner. Viewing VHDL as a description for real hardware, signals do not have any memory unless they are modeled as such, for example by using a clocked process to describe a register.

Assuming what you have above is trying to model combinational logic, it won't simulate correctly, because the sensitivity list is not complete. To be clear, it will simulate "correctly" as it is written according to VHDL language rules, but it it won't describe any sort of normal real hardware. To make it match up, consider the following minor change:

Architecture SD_BEH of SD is
signal C: std_logic;
begin
 process (A, C) -- add C to the sensitivity list
  begin 
   C<=A;
   if (C='1') then B<=A;
   else B<= '0';
   end if;
  end process;
end SD_BEH;