VHDL: Assigning elements from a 2D array to 1D array
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06-06-2021 - |
Question
I have a 2D array of records which I have to select column by column for processing. I am marshaling the column records into a column array, something like this:
col_array(0) <= ( td_array(0)(0), td_array(1)(0), td_array(2)(0), td_array(3)(0) );
Essentially an array append operation.
I have several arrays like this. Is this possible to do with a for-generate loop ?
This looks like an array append kind of operation. How do you do this ?
Addenda: Each record in the 2D array looks like:
type foo is record:
enable : std_logic;
index : std_logic_vector(7 downto 0);
cmd : std_logic_vector(2 downto 0);
end record;
So I will have interfaces like these in a row-column arrangement:
30 31 32
20 21 22
10 11 12
00 01 02
I will need to break-out the record signals by the column (using a multiplexer). So (00, 10, 20, 30) will be accessed on the output of a MUX.
Solution
Not quite sure of the actual usage you are looking for (how does the index of col_array
relate to the indices of td_array
if at all), but does this help? (I've rearranged things as a 2-d array rather than a vector of vectors)
architecture a1 of test is
type std_ulogic_2d is array(natural range <>, natural range <>) of std_ulogic;
signal td_array : std_ulogic_2d(0 to 3, 0 to 4);
signal col_array : std_ulogic_vector(td_array'range(1));
begin -- architecture a1
iloop : for i in td_array'range(1) generate
col_array(i) <= td_array(i,0);
end generate;
end architecture a1;