What is the difference between “soft reset” and “hard reset” in embedded field?

Question

In my opinion: soft reset: boots from the reset vector. hard reset: pull the electrical level of the cpu.

Answer 1

This can very from chip to chip I assume. The hard reset is probably agreed to be the reset line on the device (pin, ball, etc) when pulled in a certain direction puts some or all of the chip in reset. Soft reset, could be as simple as a branch to zero or branch to the reset vector, or it could be a register you write or a bit in a register that causes a hard reset, or perhaps something close to a hard reset, imagine a layer inside the chip, the hard reset hits the outer layer, the soft reset hits some inside layer possibly not the whole chip. for example you maybe you dont want to fall off the pcie bus so you leave that alone. Normally jtag (or some portion of it) for example shouldnt be touched by either reset. When software pulls a reset line it kills itself, who is going to release that reset? Something in hardware, many ways to solve this, but if solved with something that has a digital component to it that digital section shouldnt get hit with the reset the software has hit or you again get stuck not being able to release it.

Answer 2

A hard reset certainly means that the whole CPU chip and all its peripherals are reset. The causes for this could be many: reset pin pulled externally, clock failures, on-chip low-voltage detection, watchdog, illegal instruction traps etc etc.

A soft reset probably means a "dirty" branch to back to the reset vector, where the reset vector restores all CPU core registers including the stack. I would say that this is very questionable practice and I'm not sure what good it would do. The main problem is that all MCU peripheral hardware registers will -not- get reset to default when you do this. It is almost impossible not to make any assumptions about the reset state of all such registers, especially since the average MCU comes with 1000+ of them nowadays. So with this soft & dirty reset, you will most likely end up a behaviour like this:

subtle intermittent bugs <= my program <= complete haywire

More far-fetched, a soft reset could mean a reset caused by software. In that case it could be writing the wrong value to the watchdog register to enforce a reset, or failing to refresh the watchdog. Or it could be the execution of an illegal instruction. These will most likely cause a complete reset of the whole chip.

Answer 3

It can mean whatever the system designer wants it to mean. There is no generic definition. For example, the content of RAM may be maintained through a soft reset, but not through a hard reset, or it may simply be the difference between an external hardware reset signal and a software RESET instruction.

Answer 4

On an Intel platform, a soft reset (writing 0x4 to port 0xcf9) is a warm CPU reset, i.e. a reset while the CPU is running. A warm reset (writing 0x6 to port 0xcf9) is a host reset without a power cycle, and a hard reset (writing 0xe to port 0xcf9) is a host reset with a power cycle. A global reset is a reset of the Intel ME combined with a host reset.

A cold CPU reset is the assertion of RESET# while power is initially being supplied to the CPU. A warm CPU reset is when INIT# or RESET# occurs while V_cc and CLK remain in specified operating limits. If you just INIT# then it just flushes the BTB and TLBs and only initialises integer registers and goes to the restart MSROM routine (no longer just 0xFFFFFFF0 on UEFI systems). If you RESET# then it flushes the caches as well and initialises FP registers and not just the integer registers. This is the initial state of the registers, I think before the microcode begins. If you assert both INIT# and RESET# together then it does a BIST as well. I think in this case it reperforms the BSP selection process aka. the MP Initialisation protocol, because a BIPI is sent to all-including-self after the BIST completes, and I think it also performs BSP selection when there is no BIST i.e. just a RESET# when warm/cold (this talks about sending a BIPI after an optional BIST on reset). On modern Intel CPUs, I think RESET# is one per socket and resets all cores, and is tied to the PCH PLTRST#, whereas INIT is sent by the PCH over DMI in a PCIe VLW transaction, and is distributed on a core by core basis to the specified cores configured in a CPU register like QPIPNCB.

A warm reset is an assertion of PLTRST# by the PCH which goes to many components, and the system stays in S0. On a hard reset, the system cycles through SLP_S0# to SLP_S5# and then cycles up through SLP_S5# to SLP_S0# to end up in S0 C0 (when PLTRST# is eventually deasserted), this will result in DRAM being reset, which PLTRST# on its own doesn't do. SLP_S0 - S5# high means the CPU is in S0 C0. SLP_S0# low means it is in S0 Cx, SLP_S0# and SLP_S3# low means it is in S3, SLP_S0# and SLP_S3# and SLP_S4# low means it is in S4 and so on.

A cold reset I think is when the system boots from G3 and needs to go through PCH_RTCRST# and EC_RSMRST# before returning to the state it was in before the G3, which could be DeepSx, S5 or S4. But you will see people call the hard reset a cold reset, and the cold reset a cold boot. I would probably use the terms hard reset and cold boot. A warm boot would be a S3 resume and a cold boot would be booting from S4/S5/G3, maybe you could all S4/S5 a hard boot and G3 a cold boot.