VHDL Functions requiring additional LEs?

Question

I am creating a package that has multiple definitions similar to the following

    -- Control Register Address Type Declaration
    SUBTYPE ctrl_reg_addr_type IS std_logic_vector( ADDR_BITS-1 DOWNTO 0 );
    -- Control Register Data Type Declaration
    SUBTYPE ctrl_reg_data_type IS std_logic_vector( DATA_BITS-1 DOWNTO 0 );
    -- Control Register Type Declaration
    SUBTYPE ctrl_reg_word_type IS std_logic_vector( CTRL_BITS-1 DOWNTO 0 );

    -- Left/Right Line-In Control Type Declarations
    CONSTANT LINE_IN_VOL_BITS : integer := 5;

    SUBTYPE line_in_volume_type IS natural
    RANGE 0 TO ( 2**LINE_IN_VOL_BITS )-1;

    TYPE line_in_ctrl_type IS RECORD

        -- Left/Right Channel Line Input Volume (4:0)
        -- Registers: LINVOL/RINVOL
        -- 0x1F = +12.0dB
        -- ...  =   1.5dB steps
        -- 0x00 = -34.5dB
        -- 0x17 - 0dB (Default)
        volume : std_logic_vector( LINE_IN_VOL_BITS-1 DOWNTO 0 );
        -- Left/Right Channel Line Input Mute to ADC (7)
        -- Registers: LINMUTE/RINMUTE
        -- 0x1 = Enable Mute
        -- 0x0 = Disable Mute
        mute   : std_logic;
        -- Left/Right Channel Line Input Volume and Mute Load (8)
        -- Registers: LRINBOTH/RLINBOTH
        -- 0x1 = Enable Simultaneous Load of LINVOL/LINMUTE <-> RINVOL/RINMUTE
        -- 0x0 = Disable Simultaneous Load
        both   : std_logic;

    END RECORD line_in_ctrl_type;

I would like to use functions similar to the following to modify the fields within the record types.

    -- Left/Right Line-In Increase Volume Function Body
    FUNCTION increase_volume( ctrl : line_in_ctrl_type )
    RETURN line_in_ctrl_type IS

        VARIABLE volume : line_in_volume_type := 0;
        VARIABLE tmp    : line_in_ctrl_type;

    BEGIN

        tmp    := ctrl;
        volume := natural( to_integer( unsigned( ctrl.volume ) ) );

        IF ( volume < line_in_volume_type'HIGH ) THEN

            volume     := volume + 1;

            tmp.volume := std_logic_vector(
                              to_unsigned( volume, LINE_IN_VOL_BITS ) );

        END IF;

        RETURN ( tmp );

    END FUNCTION increase_volume;

    -- Left/Right Line-In Increase Volume Function Body
    FUNCTION increase_volume( ctrl : line_in_ctrl_type;
                              step : natural )
    RETURN line_in_ctrl_type IS

        VARIABLE volume : line_in_volume_type := 0;
        VARIABLE tmp    : line_in_ctrl_type;

    BEGIN

        tmp    := ctrl;
        volume := natural( to_integer( unsigned( ctrl.volume ) ) );

        IF ( volume < ( line_in_volume_type'HIGH - step ) ) THEN

            volume     := volume + step;

            tmp.volume := std_logic_vector(
                              to_unsigned( volume, LINE_IN_VOL_BITS ) );

        ELSE

            tmp := increase_volume( tmp );

        END IF;

        RETURN ( tmp );

    END FUNCTION increase_volume;

My questions is, will using functions similar to the examples shown, use more LEs than explicitly modifying record values.

Answer 1

Using functions in VHDL is very abstract (as VHDL should be). It can be about as far from RTL as you can get. This means asking what will be inteferred in LE's at is really difficult to determine. It mostly depends on the synthesis tools and how they pick out logical constructs.

A function is synthesised more like a macro. Each time you call it, you may end up instantiating another instance of the same logical block. How often are you calling it?

For efficient LE usage you need to write code that re-uses functional blocks. e.g. Write a generic structure read/write engine and use it once, but route the inputs and outputs from/to various places.

If you are worried about LE usage, and still want to use functions, I suggest considering if you have a big enough FPGA.

Answer 2

Using a function like that simply wraps up a load of logic in a convenient form.

If you get significantly different logic usage that way, compared to copy/pasting it all, log a bug with your synthesis vendor.