Verilog Continuous Simulation

Question

Are there special start and end keywords in verilog that will allow a simulation to continue running until an end keyword is met? I understand this would not be synthesizable; however, I only wish to use it for testing purposes. Also the $finish keyword in verilog exits modelsim.

Answer 1

$finish and $stop are the verilog system tasks to stop simulation. $finish terminates the simulation whereas $stop stops the simulation and goes to interactive mode. So you can use $stop. Even $finish should be fine since ModelSim usually asks whether you want to finish. Choose 'no' to stay in simulation mode, choosing 'yes' will exit ModelSim.