Verilog I/O reading a character

Question

I seem to have some issues anytime I try anything with I/O for verilog. Modelsim either throws function not supported for certain functions or does nothing at all. I simply need to read a file character by character and send each bit through the port. Can anyone assist

module readFile(clk,reset,dEnable,dataOut,done);
parameter size = 4;  
  //to Comply with S-block rules which is a 4x4 array will multiply by
// size so row is the number of size bits wide
parameter bits = 8*size;

input clk,reset,dEnable;
output dataOut,done;

wire [1:0] dEnable;
reg dataOut,done;
reg [7:0] addr;

integer file;
reg [31:0] c;
reg eof;

always@(posedge clk)
begin
 if(file == 0 && dEnable == 2'b10)begin      
    file = $fopen("test.kyle");      
  end    
end

always@(posedge clk) begin
  if(addr>=32 || done==1'b1)begin
    c <= $fgetc(file);
   //  c <= $getc();
    eof <= $feof(file);
    addr <= 0;
  end
end  

always@(posedge clk)
begin
  if(dEnable == 2'b10)begin
    if($feof(file))
        done <= 1'b1;
      else
        addr <= addr+1;
  end
end
//done this way because blocking statements should not really be used
always@(addr)
begin:Access_Data
  if(reset == 1'b0) begin   
    dataOut <= 1'bx;
    file <= 0;
  end
  else if(addr<32)
    dataOut <= c[31-addr];
end 

 endmodule

Answer 1

I would suggest reading the entire file at one time into an array, and then iterate over the array to output the values.

Here is a snippet of how to read bytes from a file into a SystemVerilog queue. If you need to stick to plain old Verilog you can do the same thing with a regular array.

reg [8:0] c;
byte      q[$];
int       i;

// Read file a char at a time
file = $fopen("filename", "r");
c = $fgetc(file);
while (c != 'h1ff) begin
    q.push_back(c);
    $display("Got char [%0d] 0x%0h", i++, c);
    c = $fgetc(file);
end

Note that c is defined as a 9-bit reg. The reason for is that $fgetc will return -1 when it reaches the end of the file. In order to differentiate between EOF and a valid 0xFF you need this extra bit.

I'm not familiar with $feof and don't see it in the Verilog 2001 spec, so that may be something specific to Modelsim. Or it could be the source of the "function not supported."