Effective Address Time in two level paging

Question

I am currently working on some project on OS, I know how to find EAT in single level paging which is

EAT = (MAT+TLB-AT)*a+(2*MAT+TLB-AT)*(1-a)

where

MAT is memory access time, 
TLB-AT is TLB hit time
a is hit ratio

I am trying to find out EAT in two levels, will it access memory 3-times in case of TLB-miss or four.

Answer 1

When there is a hit in TLB ==> We require {TLB access time + Access time for actual page from memory}

When there is miss in TLB ==> We require {TLB Access time + Access time for page table entry from memory + Access time for actual page from memory}

For 1-Level Paging ==> Access time for page table entry from memory

For 2-Level Paging ==> 2 * Access time for page table entry from memory

. .

For n -Level Paging ==> n * Access time for page table entry from memory

So the generalized formula can be:

EMAT= p * (TLB-Access-time + Memory Access time) + (1-p) *[TLB-Access-time +(n *Memory Access time)]

Here, p=hit ratio.

Answer 2

EAT = (%hit)(TLBAT + MAT) + (1-%hit)(TLBAT + (n+1)(MAT))

Since we have to go to memory twice for single level paging, when we add another page to the mix it simply adds one more memory read to the process.