VHDL IEEE standard lib vs. component

Question

I'm working on a VHDL project for a Xilinx FPGA, and found myself at a cross road.

I need for example to add two signals (C=A+B), and found that Xilinx has Tool that can generate a component which will do the job.

But this could also be implemented in standard VHDL: C <= A + B

If I use standard VHDL the code should be portable, but does this has lower throughput?

I mean, does the special components use DSP functions inside the FPGA ect., that makes them faster, or can the Synthesizer normally handle this?

Answer 1

Any time you can infer something do so.

Performance is very rarely impacted, especially in the case of simple things like adders and multipliers. Even RAM blocks are easy to infer for many purposes - I only tend to instantiate vendor components if I need a very specific vendor-block behaviour.

The DSP blocks will be used well if you write VHDL code for adders and multipliers of the appropriate widths (or smaller) with pipelining that matches what is available inside the block. If you want to be more advanced and use (for example) Xilinx's DSP block's opcode input then you will have to instantiate a block.