What Model-Specific Register(s) control RAM error correction on Ivy Bridge Xeon?

StackOverflow https://stackoverflow.com/questions/11274797

  •  18-06-2021
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Question

How can one determine whether error correction is active on an Ivy Bridge system? (Requires the combination of a Xeon 12xx-v2 CPU and ECC UDIMMs).

Ideally such a method would also run on systems without the requisite hardware (and return that ECC is disabled) as well as checking the memory controller configuration when the hardware is present. But for my purposes I just need it to work on a system that definitely does have ECC-capable CPU and RAM.

Normally I would use an existing tool such as MemTest86+ to check this, however it hasn't been updated to support Ivy Bridge yet.

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Solution

On IVB processors, the ECC is controlled in the chipset (CSR), and not via MSRs.

Specifically, on IVB this is in bus 1, device 15 and 29, at offset 0x7C bit 2. This should be programmed by the BIOS/MRC during start-up on platforms based on the SPD information in the DIMM reporting that the DIMMs are ECC capable (along with additional settings).

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