Question

The script mkmakefile generates the following Makefile in the builddir.

If invoked all targets are passed to the srcdir Makefile.

Can anyone explain why? Where is the magic?

lastword = $(word $(words $(1)),$(1))
makedir := $(dir $(call lastword,\$(MAKEFILE_LIST)))

MAKEARGS := -C path_to_srcdir
MAKEARGS += O=$(if $(patsubst /%,,$(makedir)),$(CURDIR)/)$(patsubst %/,%,$(makedir))

MAKEFLAGS += --no-print-directory

.PHONY: all $(MAKECMDGOALS)

all := $(filter-out all Makefile,$(MAKECMDGOALS))

all:
    $(MAKE) $(MAKEARGS) $(all)

Makefile:;

$(all): all
    @:

%/: all
    @:
Was it helpful?

Solution

Let's break it down. First, using all as both a target and a variable name is just obnoxious, something a novice coder or a code generator would do. Let's rename the variable all_targs and assume we're invoking by make Makefile foo bar baz. If we scratch a few parts that aren't relevant to the question, we get

MAKEARGS := -C path_to_srcdir

.PHONY: all $(MAKECMDGOALS)

all_targs := $(filter-out all Makefile,$(MAKECMDGOALS)) # foo bar baz

all:
    $(MAKE) $(MAKEARGS) $(all_targs)

Makefile:;

$(all_targs): all
    @: # do nothing

So we do nothing Makefile, all_targs is foo bar baz, and for those three targets we do nothing but we require all. The rule for all runs the command

make -C path_to_srcdir foo bar baz

(There are a few more twists, but that's the core of it.)

Licensed under: CC-BY-SA with attribution
Not affiliated with StackOverflow
scroll top