Make a simple circuit to dissipate power in VHDL

Question

I'm looking for ideas on something simple to write that I can use to measure power. I just need it to make sure that my power measurement is working. I'm using Xilinx ISE 14.1 on a Virtex-6. I'd like a simple circuit to write and to synthesize.

So far I tried a 1K bit counter, but that wasn't really noticeable. I tried a 9K bit counter, but ISE had trouble synthesizing it (I let it run for an hour before killing it). Now I am trying to implement large BRAMs and keeping them permanently enabled.

I need a way to restrict large vectors from getting optimized so I'd like to xor all the bits together and feed the single bit output to an LED. Is there an easy way to do this for very large vectors?

Answer 1

Here is what I came up with. I feel like it gives a good compromise for simple code and quick compile times. It is a shifter, with every other bit high, therefore every FF should be switching every clock cycle (after it has been setup). The signal could be initialized at the beginning if desired, but it shouldn't take more than a second or two, depending on your clock, to reach equilibrium. I used an led as an output to prevent optimizing of the circuit.

architecture Behavioral of top is
signal shifter : std_logic_vector(<insert size> downto 0) := (others => '0');
begin    
        process(clk)
    begin
        if(clk'event and clk = '1')then
            shift_bit <= not shift_bit;
                shifter <= shift_bit & shifter(shifter'high downto 1);
        end if;
    end process;

led <= shifter(0);
end Behavioral;

Answer 2

In VHDL 2008 you can xor a bunch of bits like this:

signal wide : std_logic_vector(1000 downto 0);
signal narrow : std_logic;

narrow <= xor wide;

Not sure if ISE supports that.

You could use a function like:

function xor_vector(i:std_logic_vector) returns std_logic is
  variable ret:std_logic:=i(i'low);
begin
  for c in i'low+1 to i'high loop
    ret := ret xor i(c);
  end loop;
  return ret;
end function;

(Untested, just typed straight in - might need syntax tweaks!)

For power dissipation, you might try feeding an alternating '1' and '0' pattern into a shift register rather than a counter - then all the bits will change every cycle. Put a reset on the shift register to ensure that the tools don't infer SRL16 to be more efficient.