VHDL synthesis warning FF/Latch has a constant value of 0
https://stackoverflow.com/questions/12171815
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I'm trying out some code that essentially involves using an FPGA and reading values from a temperature sensor.
The code is below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ds18b20 is
Port ( clk : in STD_LOGIC; --50Mhz oscillator onboard
dq : inout STD_LOGIC;
temp_h : out STD_LOGIC_VECTOR (7 downto 0);
temp_l : out STD_LOGIC_VECTOR (7 downto 0);
temperature : out STD_LOGIC_VECTOR (11 downto 0));
end ds18b20;
architecture Behavioral of ds18b20 is
--RESET : RESET AND PRESENCE PULSE
--CMD_CC : SKIP ROM [CCh]
--WRITE_BYTE : WRITE SCRATCHPAD COMMAND
--WRITE_LOW
--WRITE_HIGH
--READ_BIT :
TYPE STATE_TYPE is (RESET,CMD_CC,WRITE_BYTE,WRITE_LOW,WRITE_HIGH,READ_BIT,CMD_44,WAIT800MS,CMD_BE,GET_TMP,WAIT4MS);
signal STATE: STATE_TYPE:=RESET;
signal clk_temp : std_logic:='0';
signal clk1m : std_logic;
signal write_temp : std_logic_vector(7 downto 0) := (others => '0');
signal TMP : std_logic_vector(11 downto 0);
signal tmp_bit : std_logic;
signal WRITE_BYTE_CNT : integer range 0 to 8:=0;
signal WRITE_LOW_CNT : integer range 0 to 2:=0;
signal WRITE_HIGH_CNT : integer range 0 to 2:=0;
signal READ_BIT_CNT : integer range 0 to 3:=0;
signal GET_TMP_CNT : integer range 0 to 12:=0;
signal cnt : integer range 0 to 100001:=0;
signal count : integer range 0 to 25:=0;
signal WRITE_BYTE_FLAG : integer range 0 to 4:=0;
begin
ClkDivider: process (clk)
begin
if rising_edge(clk) then
if (count = 24) then
count <= 0;
clk_temp<= not clk_temp;
else
count <= count +1;
end if;
end if;
clk1m<=clk_temp;
end Process;
STATE_TRANSITION: process(STATE,clk)
begin
if rising_edge(clk) then
case STATE is
--Master issues RESET pulse
when RESET=>
if (cnt>=0 and cnt<500) then
dq<='0';
cnt<=cnt+1;
STATE<=RESET;
--Master waits for PRESENCE pulse
elsif (cnt>=500 and cnt<1000) then
dq<='Z';
cnt<=cnt+1;
STATE<=RESET;
elsif (cnt>=1000) then
cnt<=0;
STATE<=CMD_CC; -- SKIP ROM COMMAND STATE
end if;
when CMD_CC=> -- SKIP ROM COMMAND
write_temp<="11001100"; -- SKIP ROM BINARY COMMAND
STATE<=WRITE_BYTE; -- modified here
--Master issues write scratchpad command
when WRITE_BYTE=>
case WRITE_BYTE_CNT is
when 0 to 7=>
if (write_temp(WRITE_BYTE_CNT)='0') then
STATE<=WRITE_LOW;
else
STATE<=WRITE_HIGH;
end if;
WRITE_BYTE_CNT<=WRITE_BYTE_CNT+1;
when 8=>
if (WRITE_BYTE_FLAG=0) then -- ????0XCC??
STATE<=CMD_44; --CONVERT TEMPERATURE
WRITE_BYTE_FLAG<=1;
elsif (WRITE_BYTE_FLAG=1) then --?0X44??
STATE<=RESET;
WRITE_BYTE_FLAG<=2;
elsif (WRITE_BYTE_FLAG=2) then --????0XCC??
STATE<=CMD_BE; -- READ SCRATCHPAD
WRITE_BYTE_FLAG<=3;
elsif (WRITE_BYTE_FLAG=3) then --?0XBE??
STATE<=GET_TMP;
WRITE_BYTE_FLAG<=0;
end if;
WRITE_BYTE_CNT<=0;
end case;
when WRITE_LOW=>
case WRITE_LOW_CNT is
when 0=>
dq<='0';
if (cnt=78) then
cnt<=0;
WRITE_LOW_CNT<=1;
else
cnt<=cnt+1;
end if;
when 1=>
dq<='Z';
if (cnt=2) then
cnt<=0;
WRITE_LOW_CNT<=2;
else
cnt<=cnt+1;
end if;
when 2=>
STATE<=WRITE_BYTE;
WRITE_LOW_CNT<=0;
when others=>WRITE_LOW_CNT<=0;
end case;
when WRITE_HIGH=>
case WRITE_HIGH_CNT is
when 0=>
dq<='0';
if (cnt=8) then
cnt<=0;
WRITE_HIGH_CNT<=1;
else
cnt<=cnt+1;
end if;
when 1=>
dq<='Z';
if (cnt=72) then
cnt<=0;
WRITE_HIGH_CNT<=2;
else
cnt<=cnt+1;
end if;
when 2=>
STATE<=WRITE_BYTE;
WRITE_HIGH_CNT<=0;
when others=>WRITE_HIGH_CNT<=0;
end case;
when READ_BIT=>
case READ_BIT_CNT is
when 0=>
dq<='0';
if (cnt=4) then
READ_BIT_CNT<=1;
cnt<=0;
else
cnt<=cnt+1;
end if;
when 1=>
dq<='Z';
if (cnt=4) then
READ_BIT_CNT<=2;
cnt<=0;
else
cnt<=cnt+1;
end if;
when 2=>
TMP_BIT<=dq;
if (cnt=1) then
READ_BIT_CNT<=3;
cnt<=0;
else
cnt<=cnt+1;
end if;
when 3=>
if (cnt=45) then
cnt<=0;
READ_BIT_CNT<=0;
STATE<=GET_TMP;
else
cnt<=cnt+1;
end if;
when others=>READ_BIT_CNT<=0;
end case;
when CMD_44=> -- CONVERT TEMPERATURE
write_temp<="01000100"; -- CONVERT TEMPERATURE BINARY COMMAND
STATE<=WRITE_BYTE;
when WAIT800MS=>
if (cnt>=100000) then
STATE<=RESET;
cnt<=0;
else
cnt<=cnt+1;
STATE<=WAIT800MS;
end if;
when CMD_BE=> -- READ SCRATCHPAD
write_temp<="10111110"; -- READ SCRATHPAD BINARY COMMAND
STATE<=WRITE_BYTE;
when GET_TMP=>
case GET_TMP_CNT is
when 0 to 11=>
STATE<=READ_BIT;
TMP(GET_TMP_CNT)<=TMP_BIT;
GET_TMP_CNT<=GET_TMP_CNT+1;
when 12=>
GET_TMP_CNT<=0;
STATE<=WAIT4MS;
end case;
when WAIT4MS=>
if (cnt>=4000) then
STATE<=RESET;
cnt<=0;
else
cnt<=cnt+1;
STATE<=WAIT4MS;
end if;
when others=>STATE<=RESET;
end case;
end if;
end process;
temp_h<='0'&TMP(11 downto 5);
temp_l<="0000"&TMP(4 downto 1);
temperature <= TMP;
end Behavioral;
The warning I get is
WARNING:Xst:1293 - FF/Latch <write_temp_0> has a constant value of 0 in block <ds18b20>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <Mtridata_dq> (without init value) has a constant value of 0 in block <ds18b20>. This FF/Latch will be trimmed during the optimization process.
write_temp is a variable that holds the binary commands for the sensor. So essentially, I will be sending these commands to the sensor via the "dq" bidirectional port. Now, the warning states that write_temp is always 0 which means I can't instruct the sensor to do any operation at all since its always 0.
Could anyone please shed some light on how to overcome this? Much appreciated.
Solution
Nothing is wrong here. The warning says that write_temp_0 is always 0 - that is, the warning only applies to bit 0 of write_temp, not the other 7 bits.
This is to be expected, as you never set bit 0 of write_temp to be anything but 0. The synthesizer picks up on this, and optimizes it by simply trimming it to be a constant 0 instead of being connected to logic.
So try out the code and see if it works - if it doesn't, it's probably due to other reasons.
Also, when writing and verifying code like this, the simulator is a fantastic tool - it'll allow you to locate logic errors in your code very easily. So no reason not to get to know how to use it.
OTHER TIPS
dear same problem i am facing same problem running my code on fir, i have run your code it synthesis but due to warning it show's undefined values of your input and clk, don't assign 0 value, try to put different value like write_temp 7 to 1. i am not full expert of vhdl but when i make this change similar way i get over these warning, hope this work for you also.
I guess, this warning (FF/Latch) occurs when we forget to assign some value for some signals (or even maybe we think that it is not necessary to assign some value), especially when there are some conditions like if-else. It is expected that for all conditions we assign a value. So, it makes our code neatly and also long to repeat some assignment in every condition, but we can set an initial value for all those signals (which the FF/Latch warning refers to them) exactly after begin of a process and before if rising-edge. For example, in STATE_Transition procecc, between begin and if rising_edge, you should write write_temp <= (others=>'0').
