How to share register and bit field definitions between a device driver and the FPGA it controls

Question

Are there any good, existing software tools available to assist in generating C header files with appropriate #defines for register offsets as well as bit definitions from VHDL? If any such tools do exist, what restrictions to they place on the VHDL and how are things that should be exported designated?

So far, I've found these tools but they aren't exactly what I'm looking for:

• Vregs by Veripool
• SpectraReg by PDTi
• Bitwise by Duolog

Based upon these tools I am also interested if the proper workflow is to generate both the C and the VHDL rather than trying to go directly from VHDL (perhaps with extra tags in the comments) to C.

Answer 1

I think that final though that was bugging you is sending you in the right direction. And I'd agree with RedGlyph in that you should consider changing your work flow a little.

Have you thought about having one 'master document' for your control register information and generated everything automatically from this - RTL, testbench code, driver software headers and documentation?

I've worked on projects where the control info was kept in one master spreadsheet and everything we needed generated from this. On one family of chips, I'd written a few Python scripts to generate this stuff from CSV files exported from the spreadsheet. On another project, the spreadsheet contained macros to generate the RTL files etc that we needed.

Writing in-house scripts is all fine and good as you've total control over them and know how they work in detail. But remember that you have to spend time supporting these scripts and updating them to do new things. And consider what would happen if whoever wrote these scripts decided to go get a new job - would anyone else be familiar enough with the scripts to modify them? We're considering buying in a 3rd party tool for the reasons mentioned above.

I've also worked on projects were the documentation and header files was back-ported from the RTL -it was a nightmare. Documentation usually lagged behind the design, and often control fields would 'go missing'. I'd rather not be involved in such a project again ;)

Answer 2

You could have a look at doxygen, it supports the VHDL language and by using intermediate files you may be able to extract the information more or less easily. A by-product would be your RTL code documentation.

Another option is to build a C parser from the Yacc/Lex definitions, you can find several ones here. From there, you can parse the VHDL, extract the information (you will have to determine how to retrieve the definition of your registers) and produce a C header file. It's probably quite complicated.

But if I were you, I would really proceed differently and define the register offsets and fields in a separate file (for example, in XML), and write a small script to generate both C headers and a VHDL package, this would save you a lot of time and would be more robust from a flow point of view.

That would also help in building any documentation.

You could of course automate the process with a makefile/or in a script that prepares the database before simulation/synthesis.

Answer 3

I agree with Marty, creating in-house scripts to do this sort of thing is fun but can be problematic in the long run.

We have created a tool called IDesignSpec which is implemented as a Plugin for document editors that enable you to specify registers in a document and generate C header, VHDL, Verilog, OVM, VMM, IP-XACT, HTML, XML, SystemRDL, PDF etc. from it.

You can generate custom outputs using the TCL API. It can read in various input formats as well such as XML, IP-XACT, SystemRDL, etc.

The benefit of this approach is that your you have one specification and everything automatically keeps in sync.

Currently supported editors are : MS Word 2003 & 2007, OpenOffice, StarOffice and FrameMaker.

You can get more details at http://www.agnisys.com

Here is the complete list of solutions available:

Company name : Commercial tools (solution provided)

1. Agnisys : IDesignSpec (Plugin for Word/Excel/OpenOffice, and command line interface on Linux and Windows)
2. Atrenta : 1Team-Genesis-Registers (desktop application) --> Acquired by Synopsys. Tool not available.
3. Duolog : BitWise (Eclipse based application) --> Acquired by ARM, tool is still available.
4. PDTi : SpectaReg (Web based application) --> Tool not available any more.
5. Semifore : CSRCompiler (Command line interface)

Free/OpenSource tools

1. Veripool : VRegs
2. ParadigmWorks : Spec2Reg

Answer 4

Our design group uses SystemRDL to capture the register definitions for our Programmable System-on-Chip. We use Denali Blueprint with customized scripts for the various targets - generate the register map, PDF documentation, Verification, C header files, etc.

We are not using it to generate the RTL source yet.

http://www.spiritconsortium.org/releases/SystemRDL
http://www.google.com/search?q=SystemRDL

Answer 5

The answer might come a bit late, but we use the free netpp library and some modified XSL style sheets to generate documentation, VHDL and C source from one XML source. There's also a VHDL simulator extension that lets VHDL and C libraries exchange data to create a networking capable 'virtual FPGA'. It's called ghdlex, I don't exactly recall where it is, but you will find it somewhere on the http://section5.ch website under the netpp download area. It's a bit tricky to use, but well, it's free..

Answer 6

The real source of the shared information is your original design, so I would enter the original design in a form that is easy to process. Here are a couple of ideas...

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1. Use YAML. (Or, sigh, XML, or even a very simple DSL of your design.) Define the original data. Write scripts to dump it as VHDL and C. All the scripting languages support YAML and it's designed to be parsed with shell tools as well. You might even use simplified VHDL or C, and write a script to turn that via a simple text transformation into the corresponding C or VHDL.

2. Do it all in the C preprocessor. You could write a set of macro calls that specify register layouts. You could then have a #if or perhaps two separate .h files that define two different versions of your definition macros, one which expands into VHDL and one which expands those same definitions into C.

Answer 7

Spectareg allows you to specify the registers in one place and create multiple outputs for different environments (eg. VHDL, C, Verilog)