8 x 1 Multiplexer in verilog, syntax error 10170

Question

I am trying to create a 8 x 1 multiplexer in Verilog. When I run analysis and synthesis the code I keep getting an error. Here is my code:

// 8 x 1 line multiplexer
module KuchtaClayton_HW7_P6(output  Y, input [2:0] S, input [7:0] I);

    assign Y = (S ==3’b000) ? I[0] :
               (S ==3’b001) ? I[1] :    
               (S ==3’b010) ? I[2] :    
               (S ==3’b011) ? I[3] : 
               (S ==3’b100) ? I[4] :
               (S ==3’b101) ? I[5] :
               (S ==3’b110) ? I[6] :
               (S ==3’b111) ? I[7] : 1’bx;
endmodule

Here is the error message:

Error (10170): Verilog HDL syntax error at KuchtaClayton_HW7_P6.v(6) near text "â"; expecting ")"

There are 21 errors that are essentially the same, some look like this:

Error (10170): Verilog HDL syntax error at KuchtaClayton_HW7_P6.v(6) near text â
Error (10170): Verilog HDL syntax error at KuchtaClayton_HW7_P6.v(6) near text

I double click on them and they bring me to each assign line for Y 3 times. I am guessing I did three errors in each Boolean expression? What am I doing wrong in the assign? I am using Quartus II as my program.

Answer 1

I can only guess how on earth have you ended up with ’ character in your code as it is not that easy to type in (i.e. on Mac you have to hold Shift+Option+]). At any rate, that character is a Unicode 0xE28099 and is not a legal Verilog code. You are expected to use ASCII character ', which is 0x07 (see a table of ASCII characters).

Other than that, your syntax is OK. The only suggestion is not to use 1'bx there because with 3 bits you can represent up to 8 numbers (from 0 to 7) and thus you have a full case, so that the following code can be used:

assign Y = (S == 3'd0) ? I[0] :
           (S == 3'd1) ? I[1] :
           (S == 3'd2) ? I[2] :
           (S == 3'd3) ? I[3] :
           (S == 3'd4) ? I[4] :
           (S == 3'd5) ? I[5] :
           (S == 3'd6) ? I[6] : I[7];